 wgulian3
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61803741f8
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Merge branch 'master' into fpga_synthesis
# Conflicts:
# rtl/VX_back_end.v
# rtl/VX_gpr_stage.v
# rtl/VX_writeback.v
# rtl/simulate/test_bench.cpp
# rtl/simulate/test_bench.h
# runtime/mains/dev/Makefile
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2020-02-18 03:34:38 -05:00 |
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wgulian3
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4184980188
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verilator: run all riscv tests
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2020-02-13 13:50:57 -05:00 |
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wgulian3
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e662ef4134
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Fix verilator
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2020-02-13 13:42:43 -05:00 |
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wgulian3
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86bfa4d1e4
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Fix verilator
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2020-02-13 13:18:06 -05:00 |
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Blaise Tine
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759349f2bf
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updated README and Makefile environment settings
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2020-01-21 21:21:56 -05:00 |
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fares
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13ebe51f03
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Created a global linker file to fix descrepencies
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2019-11-21 00:24:42 -05:00 |
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fares
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53c78b905a
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Switched to g++
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2019-11-16 12:23:59 -05:00 |
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felsabbagh3
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fbf708e419
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Started simX
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2019-11-10 01:21:09 -05:00 |
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felsabbagh3
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20283e6d5d
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Verified simple mat_add matrix on RTL
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2019-11-07 18:12:15 -05:00 |
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felsabbagh3
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9e2de897f0
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Added simple_main
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2019-11-07 00:10:06 -05:00 |
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