felsabbagh3
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d31b607e01
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-28 21:43:51 -07:00 |
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felsabbagh3
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313a8e3b4b
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All cache bugs fixed - Handshaking
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2020-03-28 21:43:02 -07:00 |
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Blaise Tine
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c8a6470595
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redesigned driver demo, fixed startup code, removed --cpu from simx,
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2020-03-29 00:38:17 -04:00 |
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felsabbagh3
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5dc9493c61
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ALL tests passing - handshake
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2020-03-27 21:34:49 -07:00 |
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felsabbagh3
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614797e52f
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Migrating fpga_synthesis_temp to main
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2020-03-27 13:15:23 -07:00 |
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felsabbagh3
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39516a6f98
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Migrating fpga_synthesis_temp to main
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2020-03-27 13:15:23 -07:00 |
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felsabbagh3
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4e6de0dc38
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Fixed most of the cache issues, mat_add left
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2020-03-22 15:59:45 -07:00 |
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felsabbagh3
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5372c07b01
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Fixed most of the cache issues, mat_add left
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2020-03-22 15:59:45 -07:00 |
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felsabbagh3
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d146070275
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Fix for Single-Threaded
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2020-03-22 14:44:46 -07:00 |
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felsabbagh3
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82ea79c680
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Fix for Single-Threaded
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2020-03-22 14:44:46 -07:00 |
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Blaise Tine
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759349f2bf
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updated README and Makefile environment settings
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2020-01-21 21:21:56 -05:00 |
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fares
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f4d982b3a4
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basic rvvector example
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2019-11-21 11:22:20 -05:00 |
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fares
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13ebe51f03
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Created a global linker file to fix descrepencies
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2019-11-21 00:24:42 -05:00 |
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fares
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dcf9cd3c80
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Fixed error
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2019-11-18 13:45:49 -05:00 |
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felsabbagh3
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70651f0340
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Added a pipeline stage + fixed SM param errors
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2019-11-13 12:25:28 -05:00 |
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felsabbagh3
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ea7bd485ca
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Icache/Dcache finally done + configurability tested:
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2019-11-09 00:03:15 -05:00 |
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felsabbagh3
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8b81989bfd
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Before way logic change
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2019-11-08 18:16:40 -05:00 |
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felsabbagh3
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20283e6d5d
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Verified simple mat_add matrix on RTL
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2019-11-07 18:12:15 -05:00 |
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felsabbagh3
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5d5ad9c4ec
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FIXED BUGS
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2019-11-07 13:54:46 -05:00 |
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felsabbagh3
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58a9140f08
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Before evict_wb_old removal
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2019-11-07 13:27:38 -05:00 |
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felsabbagh3
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9e2de897f0
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Added simple_main
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2019-11-07 00:10:06 -05:00 |
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