Need to use DCACHE_NOSM_TAG_WIDTH instead of DCACHE_TAG_WIDTH; otherwise, the
`ASSIGN_VX_MEM_BUS_IF macro in VX_smem_unit.sv does assignment of packed structs
with different widths for the tag field, resulting in misaligned bit error.
This results in wrong memory addresses for the core requests.
VCS requires the output of the dpi calls to be of a type that can come
at the LHS of a procedural assignment, i.e. reg type. Seems to be a
different requirement from Verilator.
addResource() calls in Chisel BlackBox does not preserve order of the
files being included; the actual compile order for these files are
re-arranged to be in alphabetical order.
Therefore, while VX_gpu_pkg.sv has to be compiled before all the other
modules because it holds the top-level package definition, that order
cannot be ensured from Chisel. As a hacky workaround, simply `include
this file in some of the sv files whose name starts earlier than
VX_gpu_pkg in lexicographical order.
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
minor update
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cleanup
cleanup
cache bindings and memory perf refactory
minor update
minor update
hw unit tests fixes
minor update
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minor udpate
minor update
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minor updates
minor updates
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minor updates
minor updates
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