felsabbagh3
|
d0765b8fb1
|
Now Flush Routine only sends one round of snoops
|
2020-04-04 18:02:57 -07:00 |
|
felsabbagh3
|
7b4b44e5ab
|
Fixed DRAM random latency simulator
|
2020-03-31 20:33:45 -07:00 |
|
Blaise Tine
|
bca5ac5e7f
|
enable rtl sim dram stalls
|
2020-03-31 02:41:14 -04:00 |
|
Blaise Tine
|
e92c4b6774
|
enable rtl sim dram stalls
|
2020-03-31 02:38:18 -04:00 |
|
felsabbagh3
|
66a837b0df
|
SOC only 2 errors
|
2020-03-30 21:28:40 -07:00 |
|
felsabbagh3
|
88f2ad53d0
|
Fixed simulator includes
|
2020-03-30 16:43:26 -07:00 |
|
Blaise Tine
|
f6eb5dfbae
|
refactor RTL sim, added DRAM stalls support
|
2020-03-30 04:13:19 -04:00 |
|
Blaise Tine
|
2eb19e23c2
|
refactor RTL simulator
|
2020-03-30 01:53:34 -04:00 |
|
Blaise Tine
|
2d198a32c7
|
update
|
2020-03-29 23:18:26 -04:00 |
|
felsabbagh3
|
313a8e3b4b
|
All cache bugs fixed - Handshaking
|
2020-03-28 21:43:02 -07:00 |
|
Blaise Tine
|
e80fa7f233
|
missing rtl changes from OPAE
|
2020-03-27 22:37:35 -04:00 |
|
Blaise Tine
|
51fd8974a9
|
minor build fixes
|
2020-03-27 20:56:18 -04:00 |
|
Blaise Tine
|
5a5c9f3981
|
merging changes from OPAE branch making this branch
|
2020-03-27 20:19:16 -04:00 |
|
Blaise Tine
|
8763adf7bc
|
update
|
2020-03-26 04:19:53 -04:00 |
|
Blaise Tine
|
a82dd9387d
|
refactoring RTL simulator and Makefile
|
2020-03-26 04:14:36 -04:00 |
|
wgulian3
|
33d8c507df
|
Remove VX_define.h and *_synth and runtime/config.h
|
2020-03-26 04:07:17 -04:00 |
|
felsabbagh3
|
4e6de0dc38
|
Fixed most of the cache issues, mat_add left
|
2020-03-22 15:59:45 -07:00 |
|
wgulian3
|
902aa685b1
|
Add threaded -O3 build mode
|
2020-03-21 17:23:40 -04:00 |
|
felsabbagh3
|
13c6cbfa5d
|
L3 and CLUSTRING WORKS
|
2020-03-10 02:41:47 -07:00 |
|
felsabbagh3
|
e2ffbcf14b
|
MULTICORE WITH L2 WORKING
|
2020-03-09 01:17:11 -07:00 |
|
felsabbagh3
|
a539630a0a
|
Added Vortex SOC
|
2020-03-08 15:24:21 -07:00 |
|
felsabbagh3
|
2f94b26af0
|
Icache working
|
2020-03-08 13:59:35 -07:00 |
|
felsabbagh3
|
b038bdb491
|
New Cache Design Passing All Tests
|
2020-03-04 23:24:32 -08:00 |
|
felsabbagh3
|
6bf25b5b78
|
+Added icache stage -- 3rd case of AUIPC os broken?
|
2020-03-01 18:01:02 -08:00 |
|
felsabbagh3
|
be66e51613
|
Added CSRs, some Load unit tests are failing
|
2020-02-17 22:22:27 -08:00 |
|
felsabbagh3
|
a0f3f67426
|
Fixed double printing in ::io_handler
|
2020-02-17 19:47:55 -08:00 |
|
felsabbagh3
|
3a45375596
|
Fixed Verilator
|
2020-02-17 19:36:00 -08:00 |
|
wgulian3
|
4184980188
|
verilator: run all riscv tests
|
2020-02-13 13:50:57 -05:00 |
|
wgulian3
|
e662ef4134
|
Fix verilator
|
2020-02-13 13:42:43 -05:00 |
|
felsabbagh3
|
58a9140f08
|
Before evict_wb_old removal
|
2019-11-07 13:27:38 -05:00 |
|
Savan Roshan
|
e4ee2a9cbd
|
Parameterization working
|
2019-11-07 00:14:46 -05:00 |
|
Savan Roshan
|
8468e7d4d9
|
Added prefix DCACHE_
|
2019-11-05 08:33:38 -05:00 |
|
felsabbagh3
|
0ee74bc566
|
migrated 100% to modelsim
|
2019-10-27 20:08:44 -04:00 |
|
felsabbagh3
|
715982cca7
|
Modelsim Working + Simulating + dumping - Some bugs
|
2019-10-27 03:36:02 -04:00 |
|
felsabbagh3
|
c85c01e082
|
Parametized cache
|
2019-10-25 13:36:06 -04:00 |
|
felsabbagh3
|
89d0390965
|
CACHE FINALLY WORKING
|
2019-10-25 04:01:23 -04:00 |
|
felsabbagh3
|
01efe02e8b
|
CACHE WORKING just needs lb/sb
|
2019-10-25 03:03:09 -04:00 |
|
felsabbagh3
|
1e648c5819
|
FIxed first circular issue
|
2019-10-24 10:38:04 -04:00 |
|
felsabbagh3
|
1645a04b1d
|
Fixed SM + added def SYN
|
2019-10-22 15:56:30 -04:00 |
|
felsabbagh3
|
31d3d51392
|
WSPAWN imp + tested
|
2019-10-21 23:35:53 -04:00 |
|
felsabbagh3
|
b6375e76de
|
Readded IPDOM stack + SPLIT/Join tested
|
2019-10-21 21:24:49 -04:00 |
|
felsabbagh3
|
bab1852a99
|
Added Split/Join - not tested
|
2019-10-21 03:03:15 -04:00 |
|
felsabbagh3
|
4cae140ac1
|
Mem technology compiling but still reading all zeros
|
2019-10-18 16:45:42 -04:00 |
|
felsabbagh3
|
f7d826593f
|
TMC working and tested
|
2019-10-18 16:09:06 -04:00 |
|
felsabbagh3
|
6b729fd2ea
|
minor
|
2019-10-18 01:46:38 -04:00 |
|