felsabbagh3
|
89d0390965
|
CACHE FINALLY WORKING
|
2019-10-25 04:01:23 -04:00 |
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felsabbagh3
|
01efe02e8b
|
CACHE WORKING just needs lb/sb
|
2019-10-25 03:03:09 -04:00 |
|
felsabbagh3
|
1645a04b1d
|
Fixed SM + added def SYN
|
2019-10-22 15:56:30 -04:00 |
|
felsabbagh3
|
b7af8c3f34
|
Integrated Shared Memory
|
2019-10-22 05:03:47 -04:00 |
|
felsabbagh3
|
31d3d51392
|
WSPAWN imp + tested
|
2019-10-21 23:35:53 -04:00 |
|
felsabbagh3
|
b6375e76de
|
Readded IPDOM stack + SPLIT/Join tested
|
2019-10-21 21:24:49 -04:00 |
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felsabbagh3
|
bab1852a99
|
Added Split/Join - not tested
|
2019-10-21 03:03:15 -04:00 |
|
felsabbagh3
|
84f5ccb484
|
Added CSR TID/WID reads
|
2019-10-21 02:10:05 -04:00 |
|
felsabbagh3
|
4cae140ac1
|
Mem technology compiling but still reading all zeros
|
2019-10-18 16:45:42 -04:00 |
|
felsabbagh3
|
f7d826593f
|
TMC working and tested
|
2019-10-18 16:09:06 -04:00 |
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felsabbagh3
|
f7b55427b4
|
Added ISA2 infrastructure with bugs
|
2019-10-18 05:21:32 -04:00 |
|
felsabbagh3
|
6779d0fade
|
Instruction Multiplex LSU/EXU 1 cycle DONE
|
2019-10-17 22:29:21 -04:00 |
|
felsabbagh3
|
95047fcadc
|
Rename Stage that removes the need for forwarding
|
2019-10-17 00:48:54 -04:00 |
|
felsabbagh3
|
8bc3b8b0a5
|
Need to link SystemC for sc_time_stamp()
|
2019-10-14 23:25:14 -04:00 |
|
felsabbagh3
|
ee83e6d8c8
|
Moved GPR to back-end
|
2019-10-14 19:08:32 -04:00 |
|
felsabbagh3
|
e67310acfb
|
New Warp Scheduler + VCD Enable
|
2019-09-15 00:12:41 -04:00 |
|
felsabbagh3
|
fb3bc60189
|
Finalized GPR with 3-Port Structure
|
2019-09-11 14:53:32 -04:00 |
|
felsabbagh3
|
1b25b10644
|
Full Evaluation Attempt 1
|
2019-09-11 01:39:00 -04:00 |
|
felsabbagh3
|
3c3a443bd5
|
New RF with Evaluation
|
2019-09-11 01:04:23 -04:00 |
|
felsabbagh3
|
8d143d7739
|
Quartus + GPR evaluation
|
2019-09-10 20:23:01 -04:00 |
|
felsabbagh3
|
4e8da1811a
|
New GPR structure - Clone or WSPAWN
|
2019-09-09 22:17:20 -04:00 |
|
felsabbagh3
|
1882147370
|
GPR Wrapper Interface Done
|
2019-09-09 14:04:07 -04:00 |
|
felsabbagh3
|
bce9bc443c
|
GPR Wrapper in Decode
|
2019-09-09 01:03:13 -04:00 |
|
felsabbagh3
|
ecf81336db
|
Finished FE and BE high-level
|
2019-09-08 19:28:53 -04:00 |
|
felsabbagh3
|
981bf0afe5
|
FE Done
|
2019-09-08 18:36:47 -04:00 |
|
felsabbagh3
|
ad45758a35
|
Before Fetch->FE
|
2019-09-08 18:09:11 -04:00 |
|
felsabbagh3
|
c310e7381f
|
Icache interface
|
2019-09-08 17:36:09 -04:00 |
|
felsabbagh3
|
5e6804703f
|
Decode in FE
|
2019-09-08 17:24:51 -04:00 |
|
felsabbagh3
|
ac9b06bf7d
|
Before FE BE abstraction
|
2019-09-08 16:21:37 -04:00 |
|
felsabbagh3
|
fe09aafbb4
|
Interface Checkpoint 2 - Remove Lints
|
2019-09-05 19:32:37 -04:00 |
|
felsabbagh3
|
b216da5a6a
|
ram stdint + Quartus Files
|
2019-06-11 21:13:30 -07:00 |
|
felsabbagh3
|
d7afef04a9
|
Sim Work miss
|
2019-05-18 23:42:55 +04:00 |
|
felsabbagh3
|
48468ed26a
|
Proper SIMT with fine-grain scheduler implemented
|
2019-05-10 00:49:54 -07:00 |
|
felsabbagh3
|
96dac5e1ce
|
Warp + Context Aware Design - Global Stalling
|
2019-05-08 16:32:49 -07:00 |
|
felsabbagh3
|
79356c7ab1
|
Changed hierarchy + Identified private + public modules
|
2019-05-07 23:45:05 -07:00 |
|
felsabbagh3
|
191ed73415
|
Less expensive but slower fetch logic
|
2019-05-05 22:55:47 -04:00 |
|
felsabbagh3
|
f21eaec79f
|
Provisioned SM
|
2019-04-05 19:25:54 -04:00 |
|
felsabbagh3
|
166b9ae48d
|
Before Scratchpad
|
2019-04-05 17:56:05 -04:00 |
|
felsabbagh3
|
719ed25213
|
Cleanup
|
2019-03-31 16:30:37 -04:00 |
|
felsabbagh3
|
8c2ae97510
|
1 WARP 8 THREADS TESTED + FULLY WORKING
|
2019-03-31 05:21:00 -04:00 |
|
felsabbagh3
|
c83ef94d02
|
1 WARP 2 THREADS WORKING
|
2019-03-31 05:02:55 -04:00 |
|
felsabbagh3
|
52a839f84d
|
Using verilog For-loops + Passing all tests
|
2019-03-30 22:14:44 -04:00 |
|
felsabbagh3
|
99a0792a0c
|
Passing all tests with 2 threads
|
2019-03-30 03:54:20 -04:00 |
|
felsabbagh3
|
d02c3d25b7
|
sync
|
2019-03-27 13:52:13 -04:00 |
|
felsabbagh3
|
9b42e79dcf
|
Added HW threads - Infinite loop
|
2019-03-27 03:44:14 -04:00 |
|
felsabbagh3
|
cc0fb0eece
|
better use of valid signal
|
2019-03-27 00:07:59 -04:00 |
|
felsabbagh3
|
7a528c5ef2
|
Packing data wires + ALU module
|
2019-03-26 19:17:11 -04:00 |
|
felsabbagh3
|
6c64fa35f8
|
Restructure
|
2019-03-22 04:14:52 -04:00 |
|
felsabbagh3
|
097e0217de
|
Added support for MUL/DIV (Passes all tests)
|
2019-03-22 03:54:59 -04:00 |
|
felsabbagh3
|
01d142c6e6
|
rtl passing all tests
|
2019-03-22 02:44:53 -04:00 |
|