Hansung Kim
217bc189da
ifdef-guard VX_operand* to enable including both in Chisel
2024-04-15 22:06:47 -07:00
Hansung Kim
978b1fe2d0
Add operands stage with duplicated RF for rs1/2/3
2024-04-15 16:45:59 -07:00
Hansung Kim
87b966a5fa
Add perf counter for stall by any operand hazard
2024-04-15 01:01:26 -07:00
Hansung Kim
6c632200d5
Divide by per-breakdown cycle for avg stall cycles
2024-04-03 15:29:51 -07:00
Hansung Kim
62c7d1f4cf
Report any fire cycles from scoreboard as well
2024-03-29 12:23:15 -07:00
Hansung Kim
50263a5f7d
Rename sched_barrier_stalls -> perf_sched_barrier_idles
...
Sched stall by barrier is really idle because it causes !scheduler_if.valid,
which is counted as part of sched_idle.
2024-03-28 22:45:12 -07:00
Hansung Kim
dd90736382
Reformat perfcount report
2024-03-23 01:07:46 -07:00
Hansung Kim
3e6a9a6104
Expose scoreboard fires to perf interface
2024-03-23 01:06:40 -07:00
Hansung Kim
d99295793c
Periodically report perf counter; reformat operand/FU stalls
2024-03-23 00:02:02 -07:00
Hansung Kim
83e151a189
Add valid / fire / cycles-issued perf counters to dispatch
2024-03-23 00:01:15 -07:00
Hansung Kim
573be030c8
Add issue-stall-by-operand-hazard perf counters
...
Do the same reduce by + instead of OR fix for scoreboard counters.
2024-03-23 00:00:08 -07:00
Hansung Kim
dda67da84c
Add issue-stall-by-unit-busy perf counters
...
Add per-issue-width counters instead of using reduce "OR" and causing
undercounting.
2024-03-21 18:11:12 -07:00
Hansung Kim
3718a57937
Docs
2024-03-21 15:44:50 -07:00
Hansung Kim
9438862389
Add perf counter for barrier schedule stalls
2024-03-20 15:29:28 -07:00
Hansung Kim
7014ae24da
Prettier perf count reports
2024-03-19 15:25:46 -07:00
Hansung Kim
b25deb8a2e
Fix assignment for perf counters
2024-03-19 14:06:44 -07:00
Hansung Kim
df4b21507e
Customize global barrier response logic for clusters
2024-03-18 14:30:32 -07:00
Hansung Kim
2525df9c5f
Use GBAR_CLUSTER_ENABLE to guard cluster-specific modification
2024-03-17 18:24:04 -07:00
Hansung Kim
28f54bde7f
Merge remote-tracking branch 'sungwoong/master' into rtl
2024-03-14 09:15:59 -07:00
Hansung Kim
bd67ff3439
Fix creating bogus mem reqs when commit is stalled
...
When commit stage is stalled, LSU ready is deasserted for mem writes
since stores commit immediately; however, the same was not applied to
valid, creating duplicate memory write requests. Fix by guarding both
ready and valid properly.
2024-03-13 20:43:27 -07:00
Hansung Kim
8317a3fbe5
Fix fence by disallowing x-initialization instead of all-0 mask
...
Setting mem_req_mask to all-zero triggers an assertion error in
mem_scheduler. Instead, disallow initialize-by-x in instruction decode
which is the source of x-propagation. Since this seems to only happen
in VCS, define-gate it accordingly.
This reverts commit a15f4fd483
2024-03-07 17:39:18 -08:00
Hansung Kim
b63333a4ec
Merge remote-tracking branch 'upstream/master' into vortex2
2024-03-07 14:45:48 -08:00
Sungwoong Ha
3c2a266d37
second pass
2024-03-01 21:27:26 -08:00
Sungwoong Ha
a9709edae2
first pass
2024-03-01 21:05:52 -08:00
Sungwoong Ha
be7d87c82d
temp
2024-02-22 16:31:42 -08:00
Blaise Tine
8d4b6c804f
minor update
2024-02-04 20:17:12 -08:00
Blaise Tine
fe15647f98
minor update
2024-02-04 02:11:53 -08:00
Hansung Kim
48558982f7
Merge remote-tracking branch 'upstream/master' into vortex2
2024-02-01 23:35:58 -08:00
Hansung Kim
a15f4fd483
[BUGFIX] Set mem_req_mask to 0 for fence
...
Fence instructions have address field set to X's which propagates to
cache_req_ready, causing issue stalls. Fix this by setting req_mask to all-zero
so that they can be handled unaffected by x-propagation.
Setting req_valid to 0 does not fix the problem because the LSU only commits
instructions when they have a matching response coming back.
2024-02-01 22:44:33 -08:00
Blaise Tine
8ab7c590fd
disabling fetch's deadlock check when L1 caches are present
2024-01-31 06:16:54 -08:00
Blaise Tine
38b92ad592
- using SV_DPI defines to disable DPI in synthesis-based simulations
...
- fixed Intel ASE run script: run_ase.sh
2024-01-28 00:22:21 -08:00
Hansung Kim
ab55c04d0c
Add localparam for internal/external smem switch
2024-01-01 19:48:06 -08:00
Hansung Kim
b64f0c2794
Add if-stmt to switch between external/internal smem
2024-01-01 12:46:59 -08:00
Hansung Kim
144521e19c
Expose smem ports at VX_core top
...
smem_unit stays inside the core, and the two separate buses to dcache
and smem are exposed at VX_core.
Currently core_wrapper ties req valid to 1'b0, stalling kernels that
reads from sharedmem.
2023-12-31 23:57:31 -08:00
Blaise Tine
031d24e695
minor updates
2023-12-30 00:52:44 -08:00
Blaise Tine
e217bc2c23
adding tracking for SFU stalls
2023-12-28 12:12:11 -08:00
Blaise Tine
c7a81d1493
adding sockets support to simx and cache subsystem refactoring
...
minor update
minor update
minor updates
2023-12-20 15:16:12 -08:00
Blaise Tine
914b680aed
operands optimization
...
minor updates
minor updates
minor update
operands optimization
minor updates
minor updates
2023-12-20 15:07:23 -08:00
Blaise Tine
e04e026a14
profiling update
...
minor updates
2023-12-18 04:43:44 -08:00
Blaise Tine
c6845a4c8d
profiling timing optimization
...
minor update
minor update
minor update
2023-12-18 04:43:10 -08:00
Blaise Tine
f5f9e3dfdb
profiling timing optimization
2023-12-18 04:43:10 -08:00
Blaise Tine
6c7ac35054
profiling optimizations
...
minor updates
2023-12-18 04:43:00 -08:00
Blaise Tine
e5b41bcd66
wctl unit bug fix
2023-12-05 04:57:52 -08:00
root
900a1efaca
BUFFER_EX refactoring
2023-12-05 04:55:50 -08:00
Blaise Tine
e8d56dc013
minor update
2023-11-27 22:16:36 -08:00
Hansung Kim
5e5c625759
Write 0 instead of x for VX_CSR_MPM_RESERVED
...
Otherwise it makes verification hard with tools that don't process x's
well.
2023-11-27 16:06:16 -08:00
Hansung Kim
f41b50fc07
Define DBG_TRACE_CORE_PIPELINE_VCS for selective debug trace
2023-11-27 16:05:15 -08:00
Blaise Tine
24973ffca0
scoreboard optimization & profiling
2023-11-27 05:53:36 -08:00
Blaise Tine
ebec982434
minor update
2023-11-27 02:04:53 -08:00
Blaise Tine
43154cf738
minor updates
2023-11-16 23:41:59 -08:00
