4 Commits

Author	SHA1	Message	Date
wgulian3	e76d05f7ce	Fix issues quartus synthesis issues	2020-02-18 13:24:18 -05:00
wgulian3	d71f8fcc73	Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu.	2020-02-18 13:02:46 -05:00
wgulian3	0211ca4add	Add compat divide module and tb	2020-02-04 10:59:05 -05:00
wgulian3	12a4136464	quartus makefile: Support custom Quartus root location	2020-01-24 18:42:03 -05:00