Blaise Tine
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1795980a52
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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
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2020-11-21 09:47:56 -08:00 |
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Blaise Tine
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e946d976e7
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constant integration updates
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2020-11-15 08:44:57 -08:00 |
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Blaise Tine
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5d58bf3d11
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fixed l3cache hang using memory arbiter in afu
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2020-11-15 06:36:32 -08:00 |
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Blaise Tine
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203a184008
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fixed bank_core_req_abr critical path
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2020-11-08 18:25:32 -08:00 |
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Blaise Tine
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5be1d85648
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cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
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2020-11-02 01:50:12 -08:00 |
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Blaise Tine
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4bd5ee2673
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fixed rtlsim regression
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2020-10-26 12:59:58 -04:00 |
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Blaise Tine
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43ae82e788
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vlsim fix, verilator fst trace, use ram optimization
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2020-10-25 16:40:50 -07:00 |
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Blaise Tine
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4e1007e5b2
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scope refactoring
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2020-10-03 18:53:21 -04:00 |
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Blaise Tine
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990b1585f1
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CI script updates
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2020-09-20 01:27:34 -04:00 |
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Blaise Tine
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c9d38c2b80
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CI script updates
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2020-09-20 00:17:42 -04:00 |
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Blaise Tine
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a8972af51e
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Merge branch 'master' of https://github.com/vortexgpgpu/vortex-dev
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2020-09-19 22:44:27 -04:00 |
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Blaise Tine
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f6f95e0c46
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mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
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2020-09-19 14:45:42 -04:00 |
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Malik Burton
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0646180059
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Modified testbench.cpp to assume passed for
runtime and isa tests.
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2020-09-19 11:24:53 -04:00 |
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Blaise Tine
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0fab1ddd92
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adding support for verilator-driven AFU driver: vlsim
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2020-09-08 13:05:26 -04:00 |
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Blaise Tine
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112d8ab815
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adding CSR support to rtlsim driver
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2020-09-04 06:51:31 -04:00 |
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Blaise Tine
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df711986bc
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FPU DPI fallback
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2020-08-31 09:19:55 -04:00 |
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Blaise Tine
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fde3f46798
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ibuffer optimization
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2020-08-26 04:44:36 -07:00 |
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MalikBurton
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de5eb4c8b5
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updated Makefile of riscv_tests/isa
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2020-08-11 13:55:36 -04:00 |
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Blaise Tine
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688c9892d5
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2020-08-07 10:12:29 -07:00 |
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Blaise Tine
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cd29362d10
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fixed FPU handshake, optimized writeback's critical path
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2020-08-07 10:11:54 -07:00 |
|
MalikBurton
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87220f2d29
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benchmarks/riscv_tests Makefiles and modified testbench.cpp
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2020-08-07 12:54:03 -04:00 |
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Blaise Tine
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b8cd3b0b28
|
gpr pipeline optimization
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2020-08-01 12:38:30 -04:00 |
|
Blaise Tine
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31ee824862
|
merged fpu_port branch
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2020-07-31 17:13:22 -04:00 |
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Blaise Tine
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4bdab8903e
|
merge
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2020-07-31 16:49:59 -04:00 |
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Blaise Tine
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c9755a0c48
|
lkg build with pipeline + FPU fixes
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2020-07-31 09:29:44 -04:00 |
|
MalikBurton
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8abc15d266
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All runtime tests can be run from runtime/tests Makefile
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2020-07-28 18:30:20 -04:00 |
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Blaise Tine
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c2dd0a8b39
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modelsim fixes && pipeline optimization
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2020-07-28 14:20:23 -07:00 |
|
MalikBurton
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7fc7bc0cab
|
Runtime tests and riscv tests are runnable
|
2020-07-28 16:04:27 -04:00 |
|
Blaise Tine
|
8976100025
|
floating point support fixes
|
2020-07-28 04:19:46 -04:00 |
|
Blaise Tine
|
f01afcc5cd
|
floating point support fixes + riscv-tests update
|
2020-07-28 02:19:11 -04:00 |
|
Blaise Tine
|
e0a9089647
|
floating point support fixes
|
2020-07-27 16:01:56 -04:00 |
|
Blaise Tine
|
ff12393998
|
floating point support fixes
|
2020-07-27 04:53:13 -04:00 |
|
Blaise Tine
|
7c86b68977
|
pipeline refactoring: centralized issue buffer
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2020-07-26 11:21:08 -04:00 |
|
Blaise Tine
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1f63f9da25
|
new fpu implementation
|
2020-07-24 00:00:37 -04:00 |
|
Blaise Tine
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75e3c31b56
|
fpu implementation (part1)
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2020-07-23 03:18:09 -07:00 |
|
Blaise Tine
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fb44de8017
|
fixed simulator leak
|
2020-07-21 06:17:41 -07:00 |
|
Blaise Tine
|
dc7efbcfb4
|
pipeline refactoring
|
2020-07-21 05:22:47 -04:00 |
|
Blaise Tine
|
577a5791dc
|
pipeline refactoring
|
2020-07-20 08:04:04 -04:00 |
|
Blaise Tine
|
25f66e6490
|
pipeline refactoring
|
2020-07-19 05:03:47 -04:00 |
|
Blaise Tine
|
bdfacf709c
|
yosys synthesis refactoring
|
2020-07-10 18:56:41 -04:00 |
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Blaise Tine
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a70562d386
|
set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18
|
2020-06-29 08:03:19 -07:00 |
|
Blaise Tine
|
d33916f1e0
|
minor update
|
2020-06-29 00:38:59 -07:00 |
|
Blaise Tine
|
8a306de02d
|
runtime static library
|
2020-06-27 14:13:13 -04:00 |
|
Blaise Tine
|
b7d7e69f47
|
fixed assertion in lsu_unit
|
2020-06-26 00:27:55 -04:00 |
|
Blaise Tine
|
e6cc221a44
|
refactoring
|
2020-06-23 10:59:30 -07:00 |
|
Blaise Tine
|
5e718c2676
|
refactoring
|
2020-06-23 09:54:40 -07:00 |
|
Blaise Tine
|
9706a4e09d
|
minor update
|
2020-06-20 18:13:15 -04:00 |
|
Blaise Tine
|
d3440de403
|
round robin arbiter + auto buffered queue + fixed dcache arbiter
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2020-06-20 17:56:04 -04:00 |
|
Blaise Tine
|
68d9fc9a75
|
driver basic test and demo test refactoring
|
2020-06-19 09:12:07 -07:00 |
|
Blaise Tine
|
d6b0ef2b3c
|
scope refactoring + snoop invalidate
|
2020-06-12 00:04:31 -07:00 |
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