Blaise Tine
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75e3c31b56
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fpu implementation (part1)
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2020-07-23 03:18:09 -07:00 |
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Blaise Tine
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ff7f65bd1f
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opae build fixes
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2020-07-21 05:44:13 -07:00 |
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Blaise Tine
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dc7efbcfb4
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pipeline refactoring
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2020-07-21 05:22:47 -04:00 |
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Blaise Tine
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e2100e9e87
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pipeline refactoring
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2020-07-20 09:38:54 -04:00 |
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Blaise Tine
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577a5791dc
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pipeline refactoring
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2020-07-20 08:04:04 -04:00 |
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Blaise Tine
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25f66e6490
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pipeline refactoring
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2020-07-19 05:03:47 -04:00 |
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Blaise Tine
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77c3b2d45f
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lsu_unit refactoring to reduce critical path
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2020-07-10 11:23:34 -07:00 |
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Blaise Tine
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c5a64a0eed
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interfaces refactoring
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2020-07-02 19:31:55 -07:00 |
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Blaise Tine
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5d088d67c8
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Gather FPGA perf stats
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2020-07-01 09:30:12 -07:00 |
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Blaise Tine
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75d66dc335
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fix sources.txt, run_ase.sh
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2020-06-29 12:52:28 -07:00 |
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Blaise Tine
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a70562d386
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set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18
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2020-06-29 08:03:19 -07:00 |
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Blaise Tine
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27ea36440e
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multiplier fixes
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2020-06-28 14:39:18 -07:00 |
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Blaise Tine
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8302641510
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fpga fixes
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2020-06-27 14:03:20 -07:00 |
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Blaise Tine
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0a01385a2c
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few updates
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2020-06-23 09:28:24 -07:00 |
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Blaise Tine
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d6b0ef2b3c
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scope refactoring + snoop invalidate
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2020-06-12 00:04:31 -07:00 |
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Blaise Tine
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19f263c772
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scope fixes
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2020-06-09 20:49:36 -07:00 |
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Blaise Tine
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2ab90e9436
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rtl refactoring
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2020-05-05 13:31:50 -04:00 |
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Blaise Tine
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b7e892ee16
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rtl refactoring
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2020-05-05 10:46:48 -04:00 |
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Blaise Tine
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38f73af627
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update
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2020-04-21 17:50:42 -04:00 |
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