Commit Graph

21 Commits

Author SHA1 Message Date
Blaise Tine
0fab1ddd92 adding support for verilator-driven AFU driver: vlsim 2020-09-08 13:05:26 -04:00
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112d8ab815 adding CSR support to rtlsim driver 2020-09-04 06:51:31 -04:00
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0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
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c9755a0c48 lkg build with pipeline + FPU fixes 2020-07-31 09:29:44 -04:00
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5d088d67c8 Gather FPGA perf stats 2020-07-01 09:30:12 -07:00
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83a1695c73 OPAE CSR access 2020-06-30 18:14:06 -07:00
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2de61b5982 get device caps from CSRs 2020-06-30 00:08:23 -07:00
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8302641510 fpga fixes 2020-06-27 14:03:20 -07:00
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e2e1b63e14 refactor synthesis scripts + fixed quartus ram read-after-write bypass 2020-06-16 11:45:47 -07:00
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9850a1f890 minor fixes 2020-06-15 00:20:56 -07:00
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75af29febb scope refactoring 2020-06-13 11:47:28 -07:00
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4fa540575c fixed gpr_ram bug + io bus arbitration 2020-06-13 05:26:29 -07:00
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d6b0ef2b3c scope refactoring + snoop invalidate 2020-06-12 00:04:31 -07:00
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19f263c772 scope fixes 2020-06-09 20:49:36 -07:00
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457783322b scope fixes 2020-06-09 07:03:52 -07:00
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9575fe9a51 scope fixes 2020-06-08 06:54:47 -07:00
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170c88f295 scope fixes 2020-06-08 04:25:28 -07:00
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04fc34b848 minor update 2020-06-03 03:05:45 -07:00
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c2e9240b7d OPAE rtl fixes 2020-05-08 08:28:28 -07:00
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de9fc68ccc opae fixes 2020-05-06 21:14:53 -07:00
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12dc4d6874 refactoring fixes 2020-04-14 19:39:59 -04:00