Commit Graph

20 Commits

Author SHA1 Message Date
Blaise Tine
42e3b6c45d fixed lmp_mult parameters, ram init filepath 2020-09-04 07:51:46 -07:00
Blaise Tine
6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
Blaise Tine
ffd9515881 added altera fpu modules 2020-08-05 15:53:59 -07:00
Blaise Tine
d8bdaa2b4e minor update 2020-08-01 14:38:31 -07:00
Blaise Tine
c2dd0a8b39 modelsim fixes && pipeline optimization 2020-07-28 14:20:23 -07:00
Blaise Tine
7c86b68977 pipeline refactoring: centralized issue buffer 2020-07-26 11:21:08 -04:00
Blaise Tine
25f66e6490 pipeline refactoring 2020-07-19 05:03:47 -04:00
Blaise Tine
bdfacf709c yosys synthesis refactoring 2020-07-10 18:56:41 -04:00
Blaise Tine
5d088d67c8 Gather FPGA perf stats 2020-07-01 09:30:12 -07:00
Blaise Tine
27ea36440e multiplier fixes 2020-06-28 14:39:18 -07:00
Blaise Tine
baf7d3bb92 minor update 2020-06-27 17:46:45 -04:00
Blaise Tine
8302641510 fpga fixes 2020-06-27 14:03:20 -07:00
Blaise Tine
0a01385a2c few updates 2020-06-23 09:28:24 -07:00
Blaise Tine
68d9fc9a75 driver basic test and demo test refactoring 2020-06-19 09:12:07 -07:00
Blaise Tine
cf22ef2bf3 minor update 2020-05-21 13:42:08 -04:00
Blaise Tine
de9fc68ccc opae fixes 2020-05-06 21:14:53 -07:00
Blaise Tine
b7e892ee16 rtl refactoring 2020-05-05 10:46:48 -04:00
Blaise Tine
d79e36912f fix opae build 2020-04-20 12:51:42 -07:00
Blaise Tine
3cbecfcef0 opae build fix 2020-04-20 12:32:01 -07:00
Blaise Tine
e8a4923eb4 RTL code refactoring 2020-04-20 12:09:30 -04:00