9 Commits

Include renames

Author	SHA1	Message	Date
Blaise Tine	d504adb236	afu mem controller refactoring	2021-05-01 08:39:52 -07:00
Blaise Tine	95f057bc2e	fpga build refactoring	2021-04-29 06:17:28 -07:00
Blaise Tine	8410c49f53	code refactoring: DRAM => MEM renaming	2021-04-26 00:58:48 -07:00
Blaise Tine	4cb98a25a7	enabling 128-bit dram bus	2021-04-24 00:31:27 -04:00
Blaise Tine	41413a51ba	testing no-shared memory mode	2021-04-01 12:37:40 -07:00
Blaise Tine	3a266fc792	adding compiler tests to regression suite	2021-03-09 05:01:56 -08:00
Blaise Tine	907e6868cd	simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite	2021-03-08 23:58:33 -08:00
Blaise Tine	700f9eea19	moving MUL unit into ALU unit	2021-02-23 13:49:02 -08:00
Blaise Tine	6a6711b735	minor update	2021-02-04 09:11:46 -08:00