0ad87bde81
Implement WU architecture support
2026-05-25 19:25:05 +08:00
323ed7d7e9
Update Vortex core for Blackwell tensor instructions
...
- Add Blackwell tensor core support in VX_tensor_blackwell_core.sv
- Update decode, execute, and dispatch logic for new instructions
- Extend VX_define.vh and VX_types.vh with Blackwell ISA definitions
2026-05-06 14:50:54 +08:00
Hansung Kim
1410b39143
Disable trace during the very start of simulation
2024-08-13 16:01:29 -07:00
Hansung Kim
675e8ea130
Merge branch 'tensor_core' into rtl
2024-05-01 16:18:14 -07:00
Hansung Kim
62c7d1f4cf
Report any fire cycles from scoreboard as well
2024-03-29 12:23:15 -07:00
Hansung Kim
83e151a189
Add valid / fire / cycles-issued perf counters to dispatch
2024-03-23 00:01:15 -07:00
Hansung Kim
dda67da84c
Add issue-stall-by-unit-busy perf counters
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Add per-issue-width counters instead of using reduce "OR" and causing
undercounting.
2024-03-21 18:11:12 -07:00
joshua
f9b4509936
initial tensor core
2024-03-20 02:46:00 -07:00
Hansung Kim
48558982f7
Merge remote-tracking branch 'upstream/master' into vortex2
2024-02-01 23:35:58 -08:00
Blaise Tine
38b92ad592
- using SV_DPI defines to disable DPI in synthesis-based simulations
...
- fixed Intel ASE run script: run_ase.sh
2024-01-28 00:22:21 -08:00
Blaise Tine
6c7ac35054
profiling optimizations
...
minor updates
2023-12-18 04:43:00 -08:00
Hansung Kim
f41b50fc07
Define DBG_TRACE_CORE_PIPELINE_VCS for selective debug trace
2023-11-27 16:05:15 -08:00
Blaise Tine
d47cccc157
Vortex 2.0 changes:
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+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00
