Blaise Tine
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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trmontgomery
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e6a8df7be1
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miss vec is displayed
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2020-11-02 12:01:03 -05:00 |
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Carter Rene Montgomery
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9b7187441d
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updated from GT repo
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2020-09-08 18:35:47 -04:00 |
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trmontgomery
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340dd683eb
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cleanup
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2020-07-19 00:37:06 -04:00 |
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trmontgomery
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3e8179f37f
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added assert_equal to read/write test
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2020-07-19 00:34:44 -04:00 |
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trmontgomery
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ed3a0cfa4d
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added rsp map
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2020-07-19 00:08:09 -04:00 |
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trmontgomery
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2d39e0561c
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Revert "successfully invalidate req after empty"
This reverts commit 9ed2012b12.
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2020-07-18 23:58:56 -04:00 |
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trmontgomery
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9ed2012b12
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successfully invalidate req after empty
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2020-07-18 19:54:43 -04:00 |
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trmontgomery
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8ffc65f22f
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read/write test works with core_req_t
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2020-07-18 19:25:03 -04:00 |
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trmontgomery
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2fc65f4a7d
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clear req after sending
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2020-07-13 23:54:33 -04:00 |
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trmontgomery
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0e8b9ec1c2
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read and write complete
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2020-07-13 23:48:51 -04:00 |
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trmontgomery
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9f33a9feb7
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cache_sim.cpp created
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2020-06-30 17:49:43 -04:00 |
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