16 Commits

Author SHA1 Message Date
Hansung Kim
c90fe56588 More doc comments 2023-09-20 14:42:56 -07:00
Blaise Tine
d7737542e4 cache uuid support 2021-12-09 20:43:22 -05:00
Blaise Tine
18762dffce fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id, 2021-11-24 00:00:17 -05:00
Blaise Tine
bd70afa688 cache multi-porting fix - ensure per-bank uniform rw 2021-11-14 04:44:25 -05:00
Blaise Tine
e380ded5e1 Merge branch 'master' into graphics 2021-10-15 19:32:11 -07:00
Blaise Tine
9f34b2944c code refactoring for Vivado, sv2v, and yosys compatibility 2021-09-27 08:55:10 -04:00
Blaise Tine
105a24d65e shared memory optimization 2021-09-06 23:46:36 -07:00
Blaise Tine
6674e8c44a cache bank area optimization + multi-porting fix for l2/l3 caches 2021-08-28 21:34:06 -07:00
Blaise Tine
9098495153 MSHR Redesign: removed fifo replay constraints and overheads 2021-08-12 01:49:32 -07:00
Blaise Tine
7b921387bc Merge branch 'master' into graphics 2021-08-02 23:57:53 -07:00
Blaise Tine
6525dff158 fixed no shared memory bug, fixed cache debug log 2021-08-02 15:59:33 -07:00
Blaise Tine
dc322894cd bug fixes - lkg build 2021-08-01 19:21:37 -07:00
Blaise Tine
bb1ceffadd rebase master update 2021-07-30 21:03:14 -07:00
Blaise Tine
1f94a1e673 minor update 2021-07-22 14:11:59 -07:00
Blaise Tine
5c40422e4f dcache response bus optimization 2021-07-12 10:14:48 -07:00
Blaise Tine
5d2437d887 refactoring cache_config 2021-05-27 14:41:46 -07:00