Optimized cache writeback path by 1) VX_fair_arbiter and 2) Added a wb register between LSU and WB arbiter

2020-06-28 14:27:47 -07:00
parent c95d3cb22b
commit ffb760cf73
4 changed files with 91 additions and 7 deletions
--- a/hw/rtl/cache/VX_cache_core_rsp_merge.v
+++ b/hw/rtl/cache/VX_cache_core_rsp_merge.v
@@ -35,7 +35,7 @@ module VX_cache_core_rsp_merge #(

    wire [`BANK_BITS-1:0] main_bank_index;

-    VX_fixed_arbiter #(
+    VX_fair_arbiter #(
        .N(NUM_BANKS)
    ) sel_bank (
        .clk         (clk),
@@ -85,4 +85,4 @@ module VX_cache_core_rsp_merge #(
        end
    end   

-endmodule
+endmodule