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opae build fixes

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This commit is contained in:
Blaise Tine
2020-07-21 05:44:13 -07:00
parent dc7efbcfb4
commit ff7f65bd1f
17 changed files with 192 additions and 166 deletions
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10
hw/rtl/VX_mul_unit.v
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@@ -12,7 +12,7 @@ module VX_mul_unit #(
// Outputs
VX_commit_if mul_commit_if
);
wire [`NUM_THREADS-1:0][31:0] alu_result;
reg [`NUM_THREADS-1:0][31:0] alu_result;
wire [`NUM_THREADS-1:0][63:0] mul_result;
wire [`NUM_THREADS-1:0][31:0] div_result;
wire [`NUM_THREADS-1:0][31:0] rem_result;
@@ -77,6 +77,8 @@ module VX_mul_unit #(
end
end
wire stall;
reg result_avail;
reg [4:0] pending_ctr;
wire [4:0] instr_delay = `IS_DIV_OP(alu_op) ? `DIV_LATENCY : `MUL_LATENCY;
@@ -104,13 +106,13 @@ module VX_mul_unit #(
wire pipeline_stall = ~result_avail && (| mul_req_if.valid);
wire stall = (~mul_commit_if.ready && (| mul_commit_if.valid))
|| pipeline_stall;
assign stall = (~mul_commit_if.ready && (| mul_commit_if.valid))
|| pipeline_stall;
wire flush = mul_commit_if.ready && pipeline_stall;
VX_generic_register #(
.N(`NUM_THREADS + `NW_BITS + 32 + `NR_BITS + `WB_BITS + (`NUM_THREADS * 32)),
.N(`NUM_THREADS + `NW_BITS + 32 + `NR_BITS + `WB_BITS + (`NUM_THREADS * 32))
) mul_reg (
.clk (clk),
.reset (reset),