critical path optimizations
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@@ -46,17 +46,17 @@ module VX_priority_encoder #(
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.data_out (scan_lo)
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);
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VX_lzc #(
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.N (N)
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) lzc (
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.in_i (reversed),
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.cnt_o (index),
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`UNUSED_PIN (valid_o)
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);
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assign onehot = scan_lo & {(~scan_lo[N-2:0]), 1'b1};
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assign valid_out = scan_lo[N-1];
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VX_onehot_encoder #(
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.N (N)
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) onehot_encoder (
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.data_in (onehot),
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.data_out (index),
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`UNUSED_PIN (valid_out)
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);
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end else if (MODEL == 2) begin
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`IGNORE_WARNINGS_BEGIN
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@@ -66,30 +66,26 @@ module VX_priority_encoder #(
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assign higher_pri_regs[0] = 1'b0;
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assign onehot[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0];
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VX_onehot_encoder #(
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VX_lzc #(
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.N (N)
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) onehot_encoder (
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.data_in (onehot),
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.data_out (index),
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`UNUSED_PIN (valid_out)
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) lzc (
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.in_i (reversed),
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.cnt_o (index),
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.valid_o (valid_out)
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);
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assign valid_out = (| reversed);
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end else if (MODEL == 3) begin
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assign onehot = reversed & ~(reversed-1);
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VX_onehot_encoder #(
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VX_lzc #(
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.N (N)
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) onehot_encoder (
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.data_in (onehot),
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.data_out (index),
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`UNUSED_PIN (valid_out)
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) lzc (
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.in_i (reversed),
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.cnt_o (index),
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.valid_o (valid_out)
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);
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assign valid_out = (| reversed);
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end else begin
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reg [LN-1:0] index_r;
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