wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

critical path optimizations

Browse Source
This commit is contained in:
Blaise Tine
2021-09-15 04:50:45 -07:00
parent 73d102afed
commit feca2db24e
4 changed files with 49 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
hw/rtl/libs/VX_priority_encoder.v
View File

@@ -46,17 +46,17 @@ module VX_priority_encoder #(
.data_out (scan_lo)
);
VX_lzc #(
.N (N)
) lzc (
.in_i (reversed),
.cnt_o (index),
`UNUSED_PIN (valid_o)
);
assign onehot = scan_lo & {(~scan_lo[N-2:0]), 1'b1};
assign valid_out = scan_lo[N-1];
VX_onehot_encoder #(
.N (N)
) onehot_encoder (
.data_in (onehot),
.data_out (index),
`UNUSED_PIN (valid_out)
);
end else if (MODEL == 2) begin
`IGNORE_WARNINGS_BEGIN
@@ -66,30 +66,26 @@ module VX_priority_encoder #(
assign higher_pri_regs[0] = 1'b0;
assign onehot[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0];
VX_onehot_encoder #(
VX_lzc #(
.N (N)
) onehot_encoder (
.data_in (onehot),
.data_out (index),
`UNUSED_PIN (valid_out)
) lzc (
.in_i (reversed),
.cnt_o (index),
.valid_o (valid_out)
);
assign valid_out = (| reversed);
end else if (MODEL == 3) begin
assign onehot = reversed & ~(reversed-1);
VX_onehot_encoder #(
VX_lzc #(
.N (N)
) onehot_encoder (
.data_in (onehot),
.data_out (index),
`UNUSED_PIN (valid_out)
) lzc (
.in_i (reversed),
.cnt_o (index),
.valid_o (valid_out)
);
assign valid_out = (| reversed);
end else begin
reg [LN-1:0] index_r;

25
hw/rtl/libs/VX_stream_arbiter.v
View File

@@ -25,6 +25,7 @@ module VX_stream_arbiter #(
wire sel_valid;
wire sel_ready;
wire [LOG_NUM_REQS-1:0] sel_index;
wire [NUM_REQS-1:0] sel_onehot;
wire [NUM_REQS-1:0] valid_in_any;
wire [LANES-1:0] ready_in_sel;
@@ -42,13 +43,17 @@ module VX_stream_arbiter #(
end
if (TYPE == "P") begin
`UNUSED_VAR (sel_ready)
VX_lzc #(
.N (NUM_REQS)
VX_fixed_arbiter #(
.NUM_REQS (NUM_REQS),
.LOCK_ENABLE (LOCK_ENABLE)
) sel_arb (
.in_i (valid_in_any),
.cnt_o (sel_index),
.valid_o (sel_valid)
.clk (clk),
.reset (reset),
.requests (valid_in_any),
.enable (sel_ready),
.grant_valid (sel_valid),
.grant_index (sel_index),
.grant_onehot (sel_onehot)
);
end else if (TYPE == "R") begin
VX_rr_arbiter #(
@@ -61,7 +66,7 @@ module VX_stream_arbiter #(
.enable (sel_ready),
.grant_valid (sel_valid),
.grant_index (sel_index),
`UNUSED_PIN (grant_onehot)
.grant_onehot (sel_onehot)
);
end else if (TYPE == "F") begin
VX_fair_arbiter #(
@@ -74,7 +79,7 @@ module VX_stream_arbiter #(
.enable (sel_ready),
.grant_valid (sel_valid),
.grant_index (sel_index),
`UNUSED_PIN (grant_onehot)
.grant_onehot (sel_onehot)
);
end else if (TYPE == "M") begin
VX_matrix_arbiter #(
@@ -87,7 +92,7 @@ module VX_stream_arbiter #(
.enable (sel_ready),
.grant_valid (sel_valid),
.grant_index (sel_index),
`UNUSED_PIN (grant_onehot)
.grant_onehot (sel_onehot)
);
end else begin
$error ("invalid parameter");
@@ -109,7 +114,7 @@ module VX_stream_arbiter #(
end
for (genvar i = 0; i < NUM_REQS; i++) begin
assign ready_in[i] = ready_in_sel & {LANES{(sel_index == LOG_NUM_REQS'(i))}};
assign ready_in[i] = ready_in_sel & {LANES{sel_onehot[i]}};
end
for (genvar i = 0; i < LANES; ++i) begin