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minor updates

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This commit is contained in:
Blaise Tine
2021-09-05 23:05:21 -07:00
parent 377466ed1c
commit fe5112b6c1
6 changed files with 24 additions and 39 deletions
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2
hw/rtl/VX_warp_sched.v
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@@ -200,7 +200,7 @@ module VX_warp_sched #(
wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls); wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls);
VX_lzc #( VX_lzc #(
.WIDTH (`NUM_WARPS) .N (`NUM_WARPS)
) wid_select ( ) wid_select (
.in_i (ready_warps), .in_i (ready_warps),
.cnt_o (schedule_wid), .cnt_o (schedule_wid),

6
hw/rtl/cache/VX_cache.v vendored
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@@ -18,15 +18,15 @@ module VX_cache #(
parameter WORD_SIZE = 4, parameter WORD_SIZE = 4,
// Core Request Queue Size // Core Request Queue Size
parameter CREQ_SIZE = 2, parameter CREQ_SIZE = 0,
// Core Response Queue Size // Core Response Queue Size
parameter CRSQ_SIZE = 2, parameter CRSQ_SIZE = 2,
// Miss Reserv Queue Knob // Miss Reserv Queue Knob
parameter MSHR_SIZE = 8, parameter MSHR_SIZE = 8,
// Memory Response Queue Size // Memory Response Queue Size
parameter MRSQ_SIZE = 4, parameter MRSQ_SIZE = 0,
// Memory Request Queue Size // Memory Request Queue Size
parameter MREQ_SIZE = 2, parameter MREQ_SIZE = 4,
// Enable cache writeable // Enable cache writeable
parameter WRITE_ENABLE = 1, parameter WRITE_ENABLE = 1,

16
hw/rtl/libs/VX_index_buffer.v
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@@ -30,7 +30,7 @@ module VX_index_buffer #(
wire [ADDRW-1:0] free_index; wire [ADDRW-1:0] free_index;
VX_lzc #( VX_lzc #(
.WIDTH (SIZE) .N (SIZE)
) free_slots_encoder ( ) free_slots_encoder (
.in_i (free_slots_n), .in_i (free_slots_n),
.cnt_o (free_index), .cnt_o (free_index),
@@ -43,7 +43,6 @@ module VX_index_buffer #(
free_slots_n[release_addr] = 1; free_slots_n[release_addr] = 1;
end end
if (acquire_slot) begin if (acquire_slot) begin
assert(1 == free_slots[write_addr]) else $error("%t: acquiring used slot at port %d", $time, write_addr);
free_slots_n[write_addr_r] = 0; free_slots_n[write_addr_r] = 0;
end end
end end
@@ -58,12 +57,13 @@ module VX_index_buffer #(
if (release_slot) begin if (release_slot) begin
assert(0 == free_slots[release_addr]) else $error("%t: releasing invalid slot at port %d", $time, release_addr); assert(0 == free_slots[release_addr]) else $error("%t: releasing invalid slot at port %d", $time, release_addr);
end end
if (acquire_slot || full_r) begin if (acquire_slot) begin
write_addr_r <= free_index; assert(1 == free_slots[write_addr]) else $error("%t: acquiring used slot at port %d", $time, write_addr);
end end
free_slots <= free_slots_n; write_addr_r <= free_index;
empty_r <= (& free_slots_n); free_slots <= free_slots_n;
full_r <= ~free_valid; empty_r <= (& free_slots_n);
full_r <= ~free_valid;
end end
end end
@@ -74,7 +74,7 @@ module VX_index_buffer #(
) data_table ( ) data_table (
.clk (clk), .clk (clk),
.wren (acquire_slot), .wren (acquire_slot),
.waddr (write_addr), .waddr (write_addr_r),
.wdata (write_data), .wdata (write_data),
.rden (1'b1), .rden (1'b1),
.raddr (read_addr), .raddr (read_addr),

33
hw/rtl/libs/VX_shift_register.v
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@@ -13,7 +13,7 @@ module VX_shift_register_nr #(
input wire [DATAW-1:0] data_in, input wire [DATAW-1:0] data_in,
output wire [(NTAPS*DATAW)-1:0] data_out output wire [(NTAPS*DATAW)-1:0] data_out
); );
`USE_FAST_BRAM reg [DATAW-1:0] entries [DEPTH-1:0]; reg [DEPTH-1:0][DATAW-1:0] entries;
always @(posedge clk) begin always @(posedge clk) begin
if (enable) begin if (enable) begin
@@ -42,30 +42,15 @@ module VX_shift_register_wr #(
input wire [DATAW-1:0] data_in, input wire [DATAW-1:0] data_in,
output wire [(NTAPS*DATAW)-1:0] data_out output wire [(NTAPS*DATAW)-1:0] data_out
); );
`USE_FAST_BRAM reg [DEPTH-1:0][DATAW-1:0] entries; reg [DEPTH-1:0][DATAW-1:0] entries;
if (1 == DEPTH) begin always @(posedge clk) begin
if (reset) begin
always @(posedge clk) begin entries <= '0;
if (reset) begin end else if (enable) begin
entries <= (DEPTH * DATAW)'(0); for (integer i = DEPTH-1; i > 0; --i)
end else begin entries[i] <= entries[i-1];
if (enable) begin entries[0] <= data_in;
entries <= data_in;
end
end
end
end else begin
always @(posedge clk) begin
if (reset) begin
entries <= (DEPTH * DATAW)'(0);
end else begin
if (enable) begin
entries <= {entries[DEPTH-2:0], data_in};
end
end
end end
end end

2
hw/syn/quartus/pipeline/Makefile
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@@ -1,7 +1,7 @@
PROJECT = VX_pipeline PROJECT = VX_pipeline
TOP_LEVEL_ENTITY = VX_pipeline TOP_LEVEL_ENTITY = VX_pipeline
SRC_FILE = VX_pipeline.v SRC_FILE = VX_pipeline.v
RTL_DIR = ../../../rtl RTL_DIR = ../../../../rtl
FAMILY = "Arria 10" FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG DEVICE = 10AX115N3F40E2SG

2
hw/syn/quartus/project.sdc
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@@ -1,4 +1,4 @@
create_clock -name {clk} -period "220 MHz" [get_ports {clk}] create_clock -name {clk} -period "250 MHz" [get_ports {clk}]
derive_pll_clocks -create_base_clocks derive_pll_clocks -create_base_clocks
derive_clock_uncertainty derive_clock_uncertainty