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minor updates

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This commit is contained in:
Blaise Tine
2021-09-05 23:05:21 -07:00
parent 377466ed1c
commit fe5112b6c1
6 changed files with 24 additions and 39 deletions
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2
hw/syn/quartus/pipeline/Makefile
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@@ -1,7 +1,7 @@
PROJECT = VX_pipeline
TOP_LEVEL_ENTITY = VX_pipeline
SRC_FILE = VX_pipeline.v
RTL_DIR = ../../../rtl
RTL_DIR = ../../../../rtl
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG

2
hw/syn/quartus/project.sdc
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@@ -1,4 +1,4 @@
create_clock -name {clk} -period "220 MHz" [get_ports {clk}]
create_clock -name {clk} -period "250 MHz" [get_ports {clk}]
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty