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minor updates

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This commit is contained in:
Blaise Tine
2021-09-05 23:05:21 -07:00
parent 377466ed1c
commit fe5112b6c1
6 changed files with 24 additions and 39 deletions
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16
hw/rtl/libs/VX_index_buffer.v
View File

@@ -30,7 +30,7 @@ module VX_index_buffer #(
wire [ADDRW-1:0] free_index;
VX_lzc #(
.WIDTH (SIZE)
.N (SIZE)
) free_slots_encoder (
.in_i (free_slots_n),
.cnt_o (free_index),
@@ -43,7 +43,6 @@ module VX_index_buffer #(
free_slots_n[release_addr] = 1;
end
if (acquire_slot) begin
assert(1 == free_slots[write_addr]) else $error("%t: acquiring used slot at port %d", $time, write_addr);
free_slots_n[write_addr_r] = 0;
end
end
@@ -58,12 +57,13 @@ module VX_index_buffer #(
if (release_slot) begin
assert(0 == free_slots[release_addr]) else $error("%t: releasing invalid slot at port %d", $time, release_addr);
end
if (acquire_slot || full_r) begin
write_addr_r <= free_index;
if (acquire_slot) begin
assert(1 == free_slots[write_addr]) else $error("%t: acquiring used slot at port %d", $time, write_addr);
end
free_slots <= free_slots_n;
empty_r <= (& free_slots_n);
full_r <= ~free_valid;
write_addr_r <= free_index;
free_slots <= free_slots_n;
empty_r <= (& free_slots_n);
full_r <= ~free_valid;
end
end
@@ -74,7 +74,7 @@ module VX_index_buffer #(
) data_table (
.clk (clk),
.wren (acquire_slot),
.waddr (write_addr),
.waddr (write_addr_r),
.wdata (write_data),
.rden (1'b1),
.raddr (read_addr),

35
hw/rtl/libs/VX_shift_register.v
View File

@@ -13,7 +13,7 @@ module VX_shift_register_nr #(
input wire [DATAW-1:0] data_in,
output wire [(NTAPS*DATAW)-1:0] data_out
);
`USE_FAST_BRAM reg [DATAW-1:0] entries [DEPTH-1:0];
reg [DEPTH-1:0][DATAW-1:0] entries;
always @(posedge clk) begin
if (enable) begin
@@ -22,7 +22,7 @@ module VX_shift_register_nr #(
entries[0] <= data_in;
end
end
for (genvar i = 0; i < NTAPS; ++i) begin
assign data_out [i*DATAW+:DATAW] = entries [TAPS[i*DEPTHW+:DEPTHW]];
end
@@ -42,30 +42,15 @@ module VX_shift_register_wr #(
input wire [DATAW-1:0] data_in,
output wire [(NTAPS*DATAW)-1:0] data_out
);
`USE_FAST_BRAM reg [DEPTH-1:0][DATAW-1:0] entries;
reg [DEPTH-1:0][DATAW-1:0] entries;
if (1 == DEPTH) begin
always @(posedge clk) begin
if (reset) begin
entries <= (DEPTH * DATAW)'(0);
end else begin
if (enable) begin
entries <= data_in;
end
end
end
end else begin
always @(posedge clk) begin
if (reset) begin
entries <= (DEPTH * DATAW)'(0);
end else begin
if (enable) begin
entries <= {entries[DEPTH-2:0], data_in};
end
end
always @(posedge clk) begin
if (reset) begin
entries <= '0;
end else if (enable) begin
for (integer i = DEPTH-1; i > 0; --i)
entries[i] <= entries[i-1];
entries[0] <= data_in;
end
end