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Interface Checkpoint 2 - Remove Lints

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This commit is contained in:
felsabbagh3
2019-09-05 19:32:37 -04:00
parent 2d0e41db63
commit fe09aafbb4
66 changed files with 13185 additions and 23594 deletions
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146
rtl/VX_memory.v
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@@ -3,136 +3,70 @@
module VX_memory (
/* verilator lint_off UNUSED */
input wire clk,
/* verilator lint_on UNUSED */
input wire[31:0] in_alu_result[`NT_M1:0],
input wire[2:0] in_mem_read,
input wire[2:0] in_mem_write,
input wire[4:0] in_rd,
input wire[1:0] in_wb,
input wire[4:0] in_rs1,
input wire[4:0] in_rs2,
input wire[31:0] in_rd2[`NT_M1:0],
input wire[31:0] in_PC_next,
input wire[31:0] in_curr_PC,
input wire[31:0] in_branch_offset,
input wire[2:0] in_branch_type,
input wire in_valid[`NT_M1:0],
input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
input wire[`NW_M1:0] in_warp_num,
VX_mem_req_inter VX_mem_req,
VX_inst_mem_wb_inter VX_mem_wb,
output wire[31:0] out_alu_result[`NT_M1:0],
output wire[31:0] out_mem_result[`NT_M1:0],
output wire[4:0] out_rd,
output wire[1:0] out_wb,
output wire[4:0] out_rs1,
output wire[4:0] out_rs2,
output reg out_branch_dir,
output wire[31:0] out_branch_dest,
output wire out_delay,
output wire[31:0] out_PC_next,
output wire out_valid[`NT_M1:0],
output wire out_delay,
output wire out_branch_dir,
output wire[31:0] out_branch_dest,
input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
output wire[2:0] out_cache_driver_in_mem_read,
output wire[2:0] out_cache_driver_in_mem_write,
output wire out_cache_driver_in_valid[`NT_M1:0],
output wire[31:0] out_cache_driver_in_data[`NT_M1:0],
output wire[`NW_M1:0] out_warp_num
output wire[31:0] out_cache_driver_in_data[`NT_M1:0]
);
// always @(in_mem_read, in_cache_driver_out_data) begin
// if (in_mem_read == `LW_MEM_READ) begin
// $display("PC: %h ----> Received: %h for addr: ", in_curr_PC, in_cache_driver_out_data[0], in_alu_result[0]);
// end
// end
// wire[15:0] addr_0 = in_alu_result[0][31:16];
genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) begin
assign out_cache_driver_in_address[index] = VX_mem_req.alu_result[index];
assign out_cache_driver_in_data[index] = VX_mem_req.rd2[index];
assign out_cache_driver_in_valid[index] = VX_mem_req.valid[index];
// wire sm_valid[`NT_M1:0];
assign VX_mem_wb.mem_result[index] = in_cache_driver_out_data[index];
// assign sm_valid = (addr_0 != 16'hFFFF) ? in_valid : in_valid;
// wire z_valid[`NT_M1:0];
// assign z_valid = 0;
end
assign out_delay = 1'b0;
assign out_cache_driver_in_address = in_alu_result;
assign out_cache_driver_in_mem_read = in_mem_read;
assign out_cache_driver_in_mem_write = in_mem_write;
assign out_cache_driver_in_data = in_rd2;
assign out_cache_driver_in_valid = in_valid;
// always @(*) begin
// if (in_valid[0] && (in_mem_write == `SW_MEM_WRITE) && (in_alu_result[0] >= 32'h810049a0)) begin
// $display("SW$ PC: %h - Warp: %h -> [%h]%h = %h || [%h]%h = %h",in_curr_PC, in_warp_num, in_valid[0], in_alu_result[0], in_rd2[0], in_valid[1], in_alu_result[1], in_rd2[1]);
// end
// end
assign out_cache_driver_in_mem_read = VX_mem_req.mem_read;
assign out_cache_driver_in_mem_write = VX_mem_req.mem_write;
// wire[31:0] sm_out_data[`NT_M1:0];
assign VX_mem_wb.alu_result = VX_mem_req.alu_result;
assign VX_mem_wb.rd = VX_mem_req.rd;
assign VX_mem_wb.wb = VX_mem_req.wb;
assign VX_mem_wb.rs1 = VX_mem_req.rs1;
assign VX_mem_wb.rs2 = VX_mem_req.rs2;
assign VX_mem_wb.PC_next = VX_mem_req.PC_next;
assign VX_mem_wb.valid = VX_mem_req.valid;
assign VX_mem_wb.warp_num = VX_mem_req.warp_num;
// VX_shared_memory vx_shared_memory(
// .clk (clk),
// .in_address (in_alu_result),
// .in_mem_read (in_mem_read),
// .in_mem_write(in_mem_write),
// .in_valid (sm_valid),
// .in_data (in_rd2),
// .out_data (sm_out_data)
// );
reg temp_branch_dir;
// assign out_mem_result = sm_valid ? sm_out_data : in_cache_driver_out_data;
assign out_mem_result = in_cache_driver_out_data;
assign out_alu_result = in_alu_result;
assign out_rd = in_rd;
assign out_wb = in_wb;
assign out_rs1 = in_rs1;
assign out_rs2 = in_rs2;
assign out_PC_next = in_PC_next;
assign out_valid = in_valid;
assign out_warp_num = in_warp_num;
// always @(*) begin
// if (in_cache_driver_out_data[0] != 32'hbabebabe)
// begin
// $display("MEM: data read from cache_driver: %h", in_cache_driver_out_data[0]);
// end
// end
assign out_branch_dest = $signed(in_curr_PC) + ($signed(in_branch_offset) << 1);
assign out_branch_dest = $signed(VX_mem_req.curr_PC) + ($signed(VX_mem_req.branch_offset) << 1);
always @(*) begin
case(in_branch_type)
`BEQ: out_branch_dir = (in_alu_result[0] == 0) ? `TAKEN : `NOT_TAKEN;
`BNE:
begin
out_branch_dir = (in_alu_result[0] == 0) ? `NOT_TAKEN : `TAKEN;
end
`BLT: out_branch_dir = (in_alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
`BGT: out_branch_dir = (in_alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
`BLTU:
begin
out_branch_dir = (in_alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
if (in_warp_num == 1) begin
// $display("BLTU PC:%h : %d < %d = %d", in_curr_PC, in_rs1, in_rs2, (in_alu_result[0][31] == 0));
end
end
`BGTU: out_branch_dir = (in_alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
`NO_BRANCH: out_branch_dir = `NOT_TAKEN;
default: out_branch_dir = `NOT_TAKEN;
case(VX_mem_req.branch_type)
`BEQ: temp_branch_dir = (VX_mem_req.alu_result[0] == 0) ? `TAKEN : `NOT_TAKEN;
`BNE: temp_branch_dir = (VX_mem_req.alu_result[0] == 0) ? `NOT_TAKEN : `TAKEN;
`BLT: temp_branch_dir = (VX_mem_req.alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
`BGT: temp_branch_dir = (VX_mem_req.alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
`BLTU: temp_branch_dir = (VX_mem_req.alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
`BGTU: temp_branch_dir = (VX_mem_req.alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
`NO_BRANCH: temp_branch_dir = `NOT_TAKEN;
default: temp_branch_dir = `NOT_TAKEN;
endcase // in_branch_type
end
assign out_branch_dir = temp_branch_dir;
endmodule // Memory