fixed unsued parameters warnings

hw/rtl/cache/VX_bank.v

@@ -22,8 +22,6 @@ module VX_bank #(
     parameter CREQ_SIZE                     = 1, 
     // Miss Reserv Queue Knob
     parameter MSHR_SIZE                     = 1, 
-    // DRAM Response Queue Size
-    parameter DRSQ_SIZE                     = 1, 
     // DRAM Request Queue Size
     parameter DREQ_SIZE                     = 1,
 
@@ -92,6 +90,8 @@ module VX_bank #(
     input wire [`LINE_SELECT_BITS-1:0]  flush_addr
 );
 
+    `UNUSED_PARAM (CORE_TAG_ID_BITS)
+    
 `ifdef DBG_CACHE_REQ_INFO
     /* verilator lint_off UNUSED */
     wire [31:0]         debug_pc_sel, debug_pc_st0,  debug_pc_st1;
@@ -420,8 +420,7 @@ module VX_bank #(
 
     VX_miss_resrv #(
         .BANK_ID            (BANK_ID),
-        .CACHE_ID           (CACHE_ID),      
-        .CORE_TAG_ID_BITS   (CORE_TAG_ID_BITS),
+        .CACHE_ID           (CACHE_ID),
         .CACHE_LINE_SIZE    (CACHE_LINE_SIZE),
         .NUM_BANKS          (NUM_BANKS),
         .NUM_PORTS          (NUM_PORTS),

hw/rtl/cache/VX_cache.v

@@ -163,10 +163,9 @@ module VX_cache #(
     ///////////////////////////////////////////////////////////////////////////
 
     VX_flush_ctrl #( 
-        .CACHE_SIZE      (CACHE_SIZE),
+        .CACHE_SIZE (CACHE_SIZE),
         .CACHE_LINE_SIZE (CACHE_LINE_SIZE),
-        .NUM_BANKS       (NUM_BANKS),
-        .WORD_SIZE       (WORD_SIZE)
+        .NUM_BANKS  (NUM_BANKS)
     ) flush_ctrl (
         .clk       (clk),
         .reset     (reset),
@@ -294,7 +293,6 @@ module VX_cache #(
             .NUM_REQS           (NUM_REQS),
             .CREQ_SIZE          (CREQ_SIZE),
             .MSHR_SIZE          (MSHR_SIZE),
-            .DRSQ_SIZE          (DRSQ_SIZE),
             .DREQ_SIZE          (DREQ_SIZE),
             .WRITE_ENABLE       (WRITE_ENABLE),
             .CORE_TAG_WIDTH     (CORE_TAG_WIDTH),                

hw/rtl/cache/VX_data_access.v

@@ -38,6 +38,10 @@ module VX_data_access #(
     input wire [CACHE_LINE_SIZE-1:0]    byteen,
     input wire [`CACHE_LINE_WIDTH-1:0]  wdata
 );
+
+    `UNUSED_PARAM (CACHE_ID)
+    `UNUSED_PARAM (BANK_ID)
+    `UNUSED_PARAM (WORD_SIZE)
     `UNUSED_VAR (reset)
     `UNUSED_VAR (readen)
 

hw/rtl/cache/VX_flush_ctrl.v

@@ -6,9 +6,7 @@ module VX_flush_ctrl #(
     // Size of line inside a bank in bytes
     parameter CACHE_LINE_SIZE   = 1, 
     // Number of banks
-    parameter NUM_BANKS         = 1, 
-    // Size of a word in bytes
-    parameter WORD_SIZE         = 1
+    parameter NUM_BANKS         = 1
 ) (
     input wire  clk,
     input wire  reset,

hw/rtl/cache/VX_miss_resrv.v

@@ -19,9 +19,7 @@ module VX_miss_resrv #(
     parameter MSHR_SIZE         = 1, 
     parameter ALM_FULL          = (MSHR_SIZE-1),
     // core request tag size
-    parameter CORE_TAG_WIDTH    = 1,
-    // size of tag id in core request tag
-    parameter CORE_TAG_ID_BITS  = 0
+    parameter CORE_TAG_WIDTH    = 1
 ) (
     input wire clk,
     input wire reset,
@@ -58,6 +56,8 @@ module VX_miss_resrv #(
     // dequeue
     input wire                          dequeue
 );
+    `UNUSED_PARAM (CACHE_ID)
+    `UNUSED_PARAM (BANK_ID)
     localparam ADDRW = $clog2(MSHR_SIZE);
 
     reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;

hw/rtl/cache/VX_shared_mem.v

@@ -49,6 +49,8 @@ module VX_shared_mem #(
 );
 
     `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value"))
+    `UNUSED_PARAM (CACHE_ID)
+    `UNUSED_PARAM (CORE_TAG_ID_BITS)
 
     localparam CACHE_LINE_SIZE = WORD_SIZE;
 

hw/rtl/cache/VX_tag_access.v

@@ -31,6 +31,9 @@ module VX_tag_access #(
     input wire                          is_flush,
     output wire                         tag_match
 );
+
+    `UNUSED_PARAM (CACHE_ID)
+    `UNUSED_PARAM (BANK_ID)
     `UNUSED_VAR (reset)
     `UNUSED_VAR (lookup)