[rtl] Add doc comments
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@@ -9,6 +9,7 @@ module VX_execute #(
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input wire reset,
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// Dcache interface
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// NOTE(hansung): this comes out of VX_lsu_unit
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VX_dcache_req_if.master dcache_req_if,
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VX_dcache_rsp_if.slave dcache_rsp_if,
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@@ -234,4 +235,4 @@ module VX_execute #(
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&& (`INST_BR_BITS'(alu_req_if.op_type) == `INST_BR_EBREAK
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|| `INST_BR_BITS'(alu_req_if.op_type) == `INST_BR_ECALL);
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endmodule
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endmodule
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