diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index 2d12a796..1c3972b3 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -904,7 +904,6 @@ always @(posedge clk) begin if (reset) begin vx_snp_req_valid <= 0; vx_snp_req_addr <= 0; - vx_snp_req_tag <= 0; vx_snp_rsp_ready <= 0; snp_req_ctr <= 0; snp_rsp_ctr <= 0; @@ -971,7 +970,6 @@ assign cmd_csr_done = (STATE_CSR_WRITE == state) ? vx_csr_io_req_ready : vx_csr_ always @(posedge clk) begin if (reset) begin csr_io_req_sent <= 0; - cmd_csr_rdata <= 0; end else begin if (vx_csr_io_req_valid && vx_csr_io_req_ready) begin diff --git a/hw/rtl/VX_gpr_bypass.v b/hw/rtl/VX_gpr_bypass.v index 50abd8ed..fcb61320 100644 --- a/hw/rtl/VX_gpr_bypass.v +++ b/hw/rtl/VX_gpr_bypass.v @@ -36,8 +36,6 @@ module VX_gpr_bypass #( delayed_push <= 0; use_buffer <= 0; use_buffer2 <= 0; - buffer <= 0; - buffer2 <= 0; end else begin delayed_push <= push; assert(!use_buffer2 || use_buffer); diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 9e72c023..17e84694 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -61,8 +61,7 @@ module VX_gpr_stage #( wire read_fire = gpr_req_if.valid && gpr_rsp_if.ready; always @(posedge clk) begin - if (reset) begin - rs3_data <= 0; + if (reset) begin read_rs3 <= 0; end else begin if (rs3_delay) begin diff --git a/hw/rtl/VX_ibuffer.v b/hw/rtl/VX_ibuffer.v index b3e6fd9d..849d7610 100644 --- a/hw/rtl/VX_ibuffer.v +++ b/hw/rtl/VX_ibuffer.v @@ -20,7 +20,7 @@ module VX_ibuffer #( localparam ADDRW = $clog2(SIZE); localparam NWARPSW = $clog2(`NUM_WARPS+1); - reg [SIZEW-1:0] size_r [`NUM_WARPS-1:0]; + reg [`NUM_WARPS-1:0][SIZEW-1:0] size_r; wire [`NUM_WARPS-1:0] q_full; wire [`NUM_WARPS-1:0][SIZEW-1:0] q_size; diff --git a/hw/rtl/VX_instr_demux.v b/hw/rtl/VX_instr_demux.v index c545659b..299c4682 100644 --- a/hw/rtl/VX_instr_demux.v +++ b/hw/rtl/VX_instr_demux.v @@ -42,9 +42,9 @@ module VX_instr_demux ( .reset (reset), .ready_in (alu_req_ready), .valid_in (alu_req_valid), - .inst_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `ALU_BR_OP(execute_if.op_type), is_br_op, execute_if.imm, execute_if.rs1_is_PC, execute_if.rs2_is_imm, execute_if.rd, execute_if.wb, tid}), + .inst_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `ALU_BR_OP(execute_if.op_type), is_br_op, execute_if.imm, execute_if.rs1_is_PC, execute_if.rs2_is_imm, execute_if.rd, execute_if.wb, tid}), .opds_in ({gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), - .data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.is_br_op, alu_req_if.imm, alu_req_if.rs1_is_PC, alu_req_if.rs2_is_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}), + .data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.is_br_op, alu_req_if.imm, alu_req_if.rs1_is_PC, alu_req_if.rs2_is_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}), .ready_out (alu_req_if.ready), .valid_out (alu_req_if.valid) ); @@ -64,7 +64,7 @@ module VX_instr_demux ( .valid_in (lsu_req_valid), .inst_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `LSU_RW(execute_if.op_type), `LSU_BE(execute_if.op_type), execute_if.imm, execute_if.rd, execute_if.wb}), .opds_in ({gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), - .data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}), + .data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}), .ready_out (lsu_req_if.ready), .valid_out (lsu_req_if.valid) ); @@ -94,7 +94,7 @@ module VX_instr_demux ( .valid_in (csr_req_valid), .inst_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `CSR_OP(execute_if.op_type), execute_if.imm[`CSR_ADDR_BITS-1:0], execute_if.rd, execute_if.wb, 1'b0}), .opds_in ({csr_req_mask}), - .data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.csr_addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_io, csr_req_if.csr_mask}), + .data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.csr_addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_io, csr_req_if.csr_mask}), .ready_out (csr_req_if.ready), .valid_out (csr_req_if.valid) ); @@ -115,7 +115,7 @@ module VX_instr_demux ( .valid_in (mul_req_valid), .inst_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `MUL_OP(execute_if.op_type), execute_if.rd, execute_if.wb}), .opds_in ({gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), - .data_out ({mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.op_type, mul_req_if.rd, mul_req_if.wb, mul_req_if.rs1_data, mul_req_if.rs2_data}), + .data_out ({mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.op_type, mul_req_if.rd, mul_req_if.wb, mul_req_if.rs1_data, mul_req_if.rs2_data}), .ready_out (mul_req_if.ready), .valid_out (mul_req_if.valid) ); @@ -137,7 +137,7 @@ module VX_instr_demux ( .valid_in (fpu_req_valid), .inst_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `FPU_OP(execute_if.op_type), execute_if.op_mod, execute_if.rd, execute_if.wb}), .opds_in ({gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}), - .data_out ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}), + .data_out ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}), .ready_out (fpu_req_if.ready), .valid_out (fpu_req_if.valid) ); @@ -156,9 +156,9 @@ module VX_instr_demux ( .reset (reset), .ready_in (gpu_req_ready), .valid_in (gpu_req_valid), - .inst_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `GPU_OP(execute_if.op_type), execute_if.rd, execute_if.wb}), + .inst_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `GPU_OP(execute_if.op_type), execute_if.rd, execute_if.wb}), .opds_in ({gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data[0]}), - .data_out ({gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.rs1_data, gpu_req_if.rs2_data}), + .data_out ({gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.rs1_data, gpu_req_if.rs2_data}), .ready_out (gpu_req_if.ready), .valid_out (gpu_req_if.valid) ); diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index c5095bc7..fe7c9600 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -267,7 +267,6 @@ module VX_cache #( wire [SNP_REQ_TAG_WIDTH-1:0] curr_bank_snp_rsp_tag; wire curr_bank_snp_rsp_ready; - wire curr_bank_core_req_ready; wire curr_bank_miss; // Core Req diff --git a/hw/rtl/libs/VX_bypass_buffer.v b/hw/rtl/libs/VX_bypass_buffer.v index 1a002d10..843b89aa 100644 --- a/hw/rtl/libs/VX_bypass_buffer.v +++ b/hw/rtl/libs/VX_bypass_buffer.v @@ -26,7 +26,6 @@ module VX_bypass_buffer #( always @(posedge clk) begin if (reset) begin buffer_valid <= 0; - buffer <= 0; end else begin if (ready_out) begin buffer_valid <= 0; diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v index cbd9ae8c..cfcdcc77 100644 --- a/hw/rtl/libs/VX_skid_buffer.v +++ b/hw/rtl/libs/VX_skid_buffer.v @@ -21,10 +21,8 @@ module VX_skid_buffer #( always @(posedge clk) begin if (reset) begin - data_out_r <= 0; - buffer <= 0; - use_buffer <= 0; valid_out_r <= 0; + use_buffer <= 0; end else begin if (ready_out) begin use_buffer <= 0;