project directories reorganization

hw/rtl/interfaces/VX_branch_response_inter.v

@@ -0,0 +1,18 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_BRANCH_RSP
+
+`define VX_BRANCH_RSP
+
+interface VX_branch_response_inter ();
+	wire           valid_branch;
+	wire           branch_dir;
+	wire[31:0]     branch_dest;
+	wire[`NW_M1:0] branch_warp_num;
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_csr_req_inter.v

@@ -0,0 +1,24 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_CSR_REQ
+
+`define VX_CSR_REQ
+
+interface VX_csr_req_inter ();
+
+	wire[`NT_M1:0] valid;
+	wire[`NW_M1:0] warp_num;
+	wire[4:0]      rd;
+	wire[1:0]      wb;
+	wire[4:0]      alu_op;
+	wire           is_csr;
+	wire[11:0]     csr_address;
+	wire           csr_immed;
+	wire[31:0]     csr_mask;
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_csr_wb_inter.v

@@ -0,0 +1,21 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_CSR_WB_REQ
+
+`define VX_CSR_WB_REQ
+
+interface VX_csr_wb_inter ();
+
+	wire[`NT_M1:0]        valid;
+	wire[`NW_M1:0]        warp_num;
+	wire[4:0]             rd;
+	wire[1:0]             wb;
+	
+	wire[`NT_M1:0][31:0]  csr_result;
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_dcache_request_inter.v

@@ -0,0 +1,19 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_DCACHE_REQ
+
+`define VX_DCACHE_REQ
+
+interface VX_dcache_request_inter ();
+
+		wire[`NT_M1:0][31:0] out_cache_driver_in_address;
+		wire[2:0]            out_cache_driver_in_mem_read;
+		wire[2:0]            out_cache_driver_in_mem_write;
+		wire[`NT_M1:0]       out_cache_driver_in_valid;
+		wire[`NT_M1:0][31:0] out_cache_driver_in_data;
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_dcache_response_inter.v

@@ -0,0 +1,16 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_DCACHE_RSP
+
+`define VX_DCACHE_RSP
+
+interface VX_dcache_response_inter ();
+
+		wire[`NT_M1:0][31:0] in_cache_driver_out_data;
+		wire                 delay;
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_dram_req_rsp_inter.v

@@ -0,0 +1,27 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_DRAM_REQ_RSP_INTER
+
+`define VX_DRAM_REQ_RSP_INTER
+
+interface VX_dram_req_rsp_inter #(
+	parameter NUMBER_BANKS = 8,
+	parameter NUM_WORDS_PER_BLOCK = 4) ();
+
+    // Req
+    wire [31:0]                                                             o_m_evict_addr;
+    wire [31:0]                                                             o_m_read_addr;
+    wire                                                                    o_m_valid;
+    wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
+    wire                                                                    o_m_read_or_write;
+
+    // Rsp
+    wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
+    wire                                                                    i_m_ready;
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_exec_unit_req_inter.v

@@ -0,0 +1,51 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_EXE_UNIT_REQ_INTER
+
+`define VX_EXE_UNIT_REQ_INTER
+
+interface VX_exec_unit_req_inter ();
+
+	// Meta
+	wire[`NT_M1:0]       valid;
+	wire[`NW_M1:0]       warp_num;
+	wire[31:0]           curr_PC;
+	wire[31:0]           PC_next;
+
+	// Write Back Info
+	wire[4:0]            rd;
+	wire[1:0]            wb;
+
+	// Data and alu op
+	wire[`NT_M1:0][31:0] a_reg_data;
+	wire[`NT_M1:0][31:0] b_reg_data;
+	wire[4:0]            alu_op;
+	wire[4:0]            rs1;
+	wire[4:0]            rs2;
+	wire                 rs2_src;
+	wire[31:0]           itype_immed;
+	wire[19:0]           upper_immed;
+
+	// Branch type
+	wire[2:0]            branch_type;
+
+	// Jal info
+	wire                 jalQual;
+	wire                 jal;
+	wire[31:0]           jal_offset;
+
+	/* verilator lint_off UNUSED */
+	wire                 ebreak;
+	wire                 wspawn;
+	/* verilator lint_on UNUSED */
+
+	// CSR info
+	wire                 is_csr;
+	wire[11:0]           csr_address;
+	wire                 csr_immed;
+	wire[31:0]           csr_mask;
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v

@@ -0,0 +1,46 @@
+
+`include "VX_define.v"
+
+`ifndef VX_FrE_to_BE_INTER
+
+`define VX_FrE_to_BE_INTER
+
+interface VX_frE_to_bckE_req_inter ();
+
+	wire[11:0]           csr_address;
+	wire                 is_csr;
+	wire                 csr_immed;
+	wire[31:0]           csr_mask;
+	wire[4:0]            rd;
+	wire[4:0]            rs1;
+	wire[4:0]            rs2;
+	wire[4:0]            alu_op;
+	wire[1:0]            wb;
+	wire                 rs2_src;
+	wire[31:0]           itype_immed;
+	wire[2:0]            mem_read;
+	wire[2:0]            mem_write;
+	wire[2:0]            branch_type;
+	wire[19:0]           upper_immed;
+	wire[31:0]           curr_PC;
+	/* verilator lint_off UNUSED */
+	wire                 ebreak;
+	/* verilator lint_on UNUSED */
+	wire                 jalQual;
+	wire                 jal;
+	wire[31:0]           jal_offset;
+	wire[31:0]           PC_next;
+	wire[`NT_M1:0]       valid;
+	wire[`NW_M1:0]       warp_num;
+
+	// GPGPU stuff
+	wire                 is_wspawn;
+	wire                 is_tmc;   
+	wire                 is_split; 
+	wire                 is_barrier;
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_gpr_clone_inter.v

@@ -0,0 +1,18 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_GPR_CLONE_INTER
+
+`define VX_GPR_CLONE_INTER
+
+
+interface VX_gpr_clone_inter ();
+/* verilator lint_off UNUSED */
+wire           is_clone;
+wire[`NW_M1:0] warp_num;
+/* verilator lint_on UNUSED */
+endinterface
+
+
+
+`endif

hw/rtl/interfaces/VX_gpr_data_inter.v

@@ -0,0 +1,14 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_gpr_data_INTER
+
+`define VX_gpr_data_INTER
+
+interface VX_gpr_data_inter ();
+	wire[`NT_M1:0][31:0] a_reg_data;
+	wire[`NT_M1:0][31:0] b_reg_data;
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_gpr_jal_inter.v

@@ -0,0 +1,14 @@
+`include "../VX_define.v"
+`ifndef VX_GPR_JAL_INTER
+
+`define VX_GPR_JAL_INTER
+
+
+interface VX_gpr_jal_inter ();
+	wire       is_jal;
+	wire[31:0] curr_PC;
+endinterface
+
+
+
+`endif

hw/rtl/interfaces/VX_gpr_read_inter.v

@@ -0,0 +1,17 @@
+`include "../VX_define.v"
+`ifndef VX_GPR_READ
+
+`define VX_GPR_READ
+
+
+interface VX_gpr_read_inter ();
+
+	wire[4:0]      rs1;
+	wire[4:0]      rs2;
+	wire[`NW_M1:0] warp_num;
+
+endinterface
+
+
+
+`endif

hw/rtl/interfaces/VX_gpr_wspawn_inter.v

@@ -0,0 +1,18 @@
+`include "../VX_define.v"
+`ifndef VX_GPR_WSPAWN_INTER
+
+`define VX_GPR_WSPAWN_INTER
+
+
+interface VX_gpr_wspawn_inter ();
+	/* verilator lint_off UNUSED */
+	wire           is_wspawn;
+	wire[`NW_M1:0] which_wspawn;
+	// wire[`NW_M1:0] warp_num;
+	/* verilator lint_on UNUSED */
+
+endinterface
+
+
+
+`endif

hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v

@@ -0,0 +1,37 @@
+
+
+`include "../VX_cache/VX_cache_config.v"
+
+`ifndef VX_GPU_DRAM_DCACHE_REQ
+
+`define VX_GPU_DRAM_DCACHE_REQ
+
+interface VX_gpu_dcache_dram_req_inter
+    #(
+        parameter BANK_LINE_SIZE_WORDS = 2
+    )
+    ();
+
+	// DRAM Request
+    wire                              dram_req;
+    wire                              dram_req_write;
+    wire                              dram_req_read;
+    wire [31:0]                       dram_req_addr;
+    wire [31:0]                       dram_req_size;
+    wire [BANK_LINE_SIZE_WORDS-1:0][31:0]  dram_req_data;
+
+    // Snoop
+    wire                              dram_because_of_snp;
+    wire                              dram_snp_full;
+
+    // DRAM Cache can't accept response
+    wire                              dram_fill_accept;
+
+
+    // DRAM Cache can't accept request
+    wire                              dram_req_delay;
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v

@@ -0,0 +1,23 @@
+
+
+
+`include "../VX_cache/VX_cache_config.v"
+
+`ifndef VX_GPU_DRAM_DCACHE_RES
+
+`define VX_GPU_DRAM_DCACHE_RES
+
+interface VX_gpu_dcache_dram_res_inter
+	#(
+		parameter BANK_LINE_SIZE_WORDS = 2
+	)
+	();
+	// DRAM Rsponse
+    wire                                   dram_fill_rsp;
+    wire [31:0]                            dram_fill_rsp_addr;
+    wire [BANK_LINE_SIZE_WORDS-1:0][31:0]  dram_fill_rsp_data;
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_gpu_dcache_req_inter.v

@@ -0,0 +1,32 @@
+
+
+`include "../VX_cache/VX_cache_config.v"
+
+`ifndef VX_GPU_DCACHE_REQ
+
+`define VX_GPU_DCACHE_REQ
+
+interface VX_gpu_dcache_req_inter
+	#(
+	parameter NUMBER_REQUESTS               = 32
+	)
+	();
+
+	// Core Request
+	wire [NUMBER_REQUESTS-1:0]         core_req_valid;
+	wire [NUMBER_REQUESTS-1:0][31:0]   core_req_addr;
+	wire [NUMBER_REQUESTS-1:0][31:0]   core_req_writedata;
+	wire [NUMBER_REQUESTS-1:0][2:0]    core_req_mem_read;
+	wire [NUMBER_REQUESTS-1:0][2:0]    core_req_mem_write;
+    wire [4:0]                         core_req_rd;
+    wire [NUMBER_REQUESTS-1:0][1:0]    core_req_wb;
+    wire [`NW_M1:0]                    core_req_warp_num;
+    wire [31:0]                        core_req_pc;
+
+    // Can't WB
+    wire                               core_no_wb_slot;
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_gpu_dcache_res_inter.v

@@ -0,0 +1,29 @@
+
+
+`include "../VX_cache/VX_cache_config.v"
+
+`ifndef VX_GPU_DCACHE_RES
+
+`define VX_GPU_DCACHE_RES
+
+interface VX_gpu_dcache_res_inter
+	#(
+		parameter NUMBER_REQUESTS = 32
+	)
+	();
+
+	// Cache WB
+    wire [NUMBER_REQUESTS-1:0]        core_wb_valid;
+    wire [4:0]                        core_wb_req_rd;
+    wire [1:0]                        core_wb_req_wb;
+    wire [`NW_M1:0]                   core_wb_warp_num;
+    wire [NUMBER_REQUESTS-1:0][31:0]  core_wb_readdata;
+    wire [NUMBER_REQUESTS-1:0][31:0]  core_wb_pc;
+
+    // Cache Full
+    wire                              delay_req;
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v

@@ -0,0 +1,18 @@
+
+
+
+`include "../VX_cache/VX_cache_config.v"
+
+`ifndef VX_GPU_SNP_REQ
+
+`define VX_GPU_SNP_REQ
+
+interface VX_gpu_dcache_snp_req_inter ();
+	// Snoop Req
+    wire                              snp_req;
+    wire [31:0]                       snp_req_addr;
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_gpu_inst_req_inter.v

@@ -0,0 +1,27 @@
+`include "../VX_define.v"
+
+`ifndef VX_GPU_INST_REQ_IN
+
+`define VX_GPU_INST_REQ_IN
+
+interface VX_gpu_inst_req_inter();
+
+	wire[`NT_M1:0]       valid;
+	wire[`NW_M1:0]       warp_num;
+	wire                 is_wspawn;
+	wire                 is_tmc;   
+	wire                 is_split; 
+
+	wire                 is_barrier;
+
+	wire[31:0]           pc_next;
+
+	wire[`NT_M1:0][31:0] a_reg_data;
+	wire[31:0]           rd2;
+
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_gpu_snp_req_rsp.v

@@ -0,0 +1,20 @@
+`include "../VX_cache/VX_cache_config.v"
+
+`ifndef VX_GPU_SNP_REQ_RSP
+
+`define VX_GPU_SNP_REQ_RSP
+
+interface VX_gpu_snp_req_rsp
+	();
+
+	// Snoop request
+	wire        snp_req;
+	wire[31:0]  snp_req_addr;
+
+	// Snoop Response
+	wire        snp_delay;
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_icache_request_inter.v

@@ -0,0 +1,19 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_ICACHE_REQ
+
+`define VX_ICACHE_REQ
+
+interface VX_icache_request_inter ();
+
+	wire[31:0]          pc_address;
+	wire[2:0]           out_cache_driver_in_mem_read;
+	wire[2:0]           out_cache_driver_in_mem_write;
+	wire       			out_cache_driver_in_valid;
+	wire[31:0] 			out_cache_driver_in_data;
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_icache_response_inter.v

@@ -0,0 +1,18 @@
+`include "../VX_define.v"
+
+`ifndef VX_ICACHE_RSP
+
+`define VX_ICACHE_RSP
+
+interface VX_icache_response_inter ();
+
+	// wire ready;
+	// wire stall;
+	wire[31:0] instruction;
+	wire       delay;
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_inst_exec_wb_inter.v

@@ -0,0 +1,21 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_EXEC_UNIT_WB_INST_INTER
+
+`define VX_EXEC_UNIT_WB_INST_INTER
+
+interface VX_inst_exec_wb_inter ();
+
+	wire[`NT_M1:0][31:0]  alu_result; 
+	wire[31:0]            exec_wb_pc;
+	wire[4:0]      		  rd;
+	wire[1:0]      		  wb;
+	wire[`NT_M1:0]        wb_valid;
+	wire[`NW_M1:0]        wb_warp_num;
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_inst_mem_wb_inter.v

@@ -0,0 +1,21 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_MEM_WB_INST_INTER
+
+`define VX_MEM_WB_INST_INTER
+
+interface VX_inst_mem_wb_inter ();
+
+	wire[`NT_M1:0][31:0]  loaded_data; 
+	wire[31:0]            mem_wb_pc;
+	wire[4:0]      		  rd;
+	wire[1:0]      		  wb;
+	wire[`NT_M1:0]        wb_valid;
+	wire[`NW_M1:0]        wb_warp_num;
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_inst_meta_inter.v

@@ -0,0 +1,16 @@
+`include "../VX_define.v"
+
+`ifndef VX_F_D_INTER
+
+`define VX_F_D_INTER
+
+interface VX_inst_meta_inter ();
+	wire[31:0]       instruction;
+	wire[31:0]       inst_pc;
+	wire[`NW_M1:0]   warp_num;
+	wire[`NT_M1:0]   valid;
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_jal_response_inter.v

@@ -0,0 +1,17 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_JAL_RSP
+
+`define VX_JAL_RSP
+
+interface VX_jal_response_inter ();
+
+	wire           jal;
+	wire[31:0]     jal_dest;
+	wire[`NW_M1:0] jal_warp_num;
+	
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_join_inter.v

@@ -0,0 +1,17 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_JOIN_INTER
+
+`define VX_JOIN_INTER
+
+interface VX_join_inter ();
+
+	wire            is_join;
+	wire[`NW_M1:0]  join_warp_num;
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_lsu_req_inter.v

@@ -0,0 +1,24 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_LSU_REQ_INTER
+
+`define VX_LSU_REQ_INTER
+
+interface VX_lsu_req_inter ();
+
+	wire[`NT_M1:0]       valid;
+	wire[31:0]           lsu_pc;
+	wire[`NW_M1:0]       warp_num;
+	wire[`NT_M1:0][31:0] store_data;
+	wire[`NT_M1:0][31:0] base_address; // A reg data
+	wire[31:0]           offset;       // itype_immed
+	wire[2:0]            mem_read; 
+	wire[2:0]            mem_write;
+	wire[4:0]            rd;
+	wire[1:0]            wb;
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_mem_req_inter.v

@@ -0,0 +1,28 @@
+`include "../VX_define.v"
+
+`ifndef VX_MEM_REQ_IN
+
+`define VX_MEM_REQ_IN
+
+interface VX_mem_req_inter ();
+
+	wire[`NT_M1:0][31:0] alu_result;
+	wire[2:0]            mem_read; 
+	wire[2:0]            mem_write;
+	wire[4:0]            rd;
+	wire[1:0]            wb;
+	wire[4:0]            rs1;
+	wire[4:0]            rs2;
+	wire[`NT_M1:0][31:0] rd2;
+	wire[31:0]           PC_next;
+	wire[31:0]           curr_PC;
+	wire[31:0]           branch_offset;
+	wire[2:0]            branch_type; 
+	wire[`NT_M1:0]       valid;
+	wire[`NW_M1:0]       warp_num;
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_mw_wb_inter.v

@@ -0,0 +1,22 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_MW_WB_INTER
+
+`define VX_MW_WB_INTER
+
+interface VX_mw_wb_inter ();
+
+		wire[`NT_M1:0][31:0] alu_result;
+		wire[`NT_M1:0][31:0] mem_result;
+		wire[4:0]            rd;
+		wire[1:0]            wb;
+		wire[31:0]           PC_next;
+		wire[`NT_M1:0]       valid;
+		wire [`NW_M1:0]      warp_num;
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_warp_ctl_inter.v

@@ -0,0 +1,36 @@
+
+`include "../VX_define.v"
+
+`ifndef VX_WARP_CTL_INTER
+
+`define VX_WARP_CTL_INTER
+
+interface VX_warp_ctl_inter ();
+
+	wire[`NW_M1:0] warp_num;
+	wire           change_mask;
+	wire[`NT_M1:0] thread_mask;
+
+	wire           wspawn;
+	wire[31:0]     wspawn_pc;
+	wire[`NW-1:0]  wspawn_new_active;
+
+	wire           ebreak;
+
+	// barrier
+	wire              is_barrier;
+	wire[31:0]        barrier_id;
+	wire[$clog2(`NW):0]  num_warps;
+
+	wire           is_split;
+	wire           dont_split;
+	wire[`NW_M1:0] split_warp_num;
+	wire[`NT_M1:0] split_new_mask;
+	wire[`NT_M1:0] split_later_mask;
+	wire[31:0]     split_save_pc;
+
+
+endinterface
+
+
+`endif

hw/rtl/interfaces/VX_wb_inter.v

@@ -0,0 +1,21 @@
+`include "../VX_define.v"
+
+`ifndef VX_WB_INTER
+
+`define VX_WB_INTER
+
+
+interface VX_wb_inter ();
+
+	wire[`NT_M1:0][31:0]  write_data; 
+	wire[31:0]            wb_pc;
+	wire[4:0]      		  rd;
+	wire[1:0]      		  wb;
+	wire[`NT_M1:0]        wb_valid;
+	wire[`NW_M1:0]        wb_warp_num;
+
+endinterface
+
+
+
+`endif

hw/rtl/interfaces/VX_wstall_inter.v

@@ -0,0 +1,15 @@
+`include "../VX_define.v"
+
+`ifndef VX_WSTALL_INTER
+
+`define VX_WSTALL_INTER
+
+
+interface VX_wstall_inter();
+	wire           wstall;
+	wire[`NW_M1:0] warp_num;
+endinterface
+
+
+
+`endif