project directories reorganization
This commit is contained in:
Blaise Tine
138
hw/rtl/compat/VX_divide.v
Normal file
138
hw/rtl/compat/VX_divide.v
Normal file
@@ -0,0 +1,138 @@
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module VX_divide
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#(
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parameter WIDTHN=1,
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parameter WIDTHD=1,
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parameter NREP="UNSIGNED",
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parameter DREP="UNSIGNED",
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parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
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parameter PIPELINE=0
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)
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(
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input clock, aclr, clken,
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input [WIDTHN-1:0] numer,
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input [WIDTHD-1:0] denom,
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output reg [WIDTHN-1:0] quotient,
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output reg [WIDTHD-1:0] remainder
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);
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// synthesis read_comments_as_HDL on
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// localparam IMPL = "quartus";
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// synthesis read_comments_as_HDL off
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// altera translate_off
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localparam IMPL="fallback";
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// altera translate_on
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generate
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if (NREP != DREP) begin
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different_nrep_drep_not_yet_supported non_existing_module();
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end
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if (IMPL == "quartus") begin
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localparam lpm_speed=SPEED == "HIGHEST" ? 9:5;
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lpm_divide#(
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.LPM_WIDTHN(WIDTHN),
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.LPM_WIDTHD(WIDTHD),
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.LPM_NREPRESENTATION(NREP),
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.LPM_DREPRESENTATION(DREP),
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.LPM_PIPELINE(PIPELINE),
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.LPM_REMAINDERPOSITIVE("FALSE"), // emulate verilog % operator
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.MAXIMIZE_SPEED(lpm_speed)
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) quartus_divider(
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.clock(clock),
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.aclr(aclr),
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.clken(clken),
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.numer(numer),
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.denom(denom),
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.quotient(quotient),
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.remain(remainder)
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);
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end
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else begin
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wire [WIDTHN-1:0] numer_pipe_end;
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wire [WIDTHD-1:0] denom_pipe_end;
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if (PIPELINE == 0) begin
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assign numer_pipe_end = numer;
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assign denom_pipe_end = denom;
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end else begin
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reg [WIDTHN-1:0] numer_pipe [0:PIPELINE-1];
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reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
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genvar pipe_stage;
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for (pipe_stage = 0; pipe_stage < PIPELINE-1; pipe_stage = pipe_stage+1) begin : pipe_stages
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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numer_pipe[pipe_stage+1] <= 0;
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denom_pipe[pipe_stage+1] <= 0;
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end
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else if (clken) begin
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numer_pipe[pipe_stage+1] <= numer_pipe[pipe_stage];
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denom_pipe[pipe_stage+1] <= denom_pipe[pipe_stage];
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end
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end
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end
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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numer_pipe[0] <= 0;
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denom_pipe[0] <= 0;
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end
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else if (clken) begin
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numer_pipe[0] <= numer;
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denom_pipe[0] <= denom;
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end
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end
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assign numer_pipe_end = numer_pipe[PIPELINE-1];
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assign denom_pipe_end = denom_pipe[PIPELINE-1];
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end
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/* * * * * * * * * * * * * * * * * * * * * * */
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/* Do the actual fallback computation here */
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/* * * * * * * * * * * * * * * * * * * * * * */
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if (NREP == "SIGNED") begin
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/*VX_divide_internal_signed #(
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.WIDTHN,
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.WIDTHD
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)div(
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.numer(numer_pipe_end),
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.denom(denom_pipe_end),
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.quotient,
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.remainder
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);*/
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always @(*) begin
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if (denom_pipe_end == 0) begin
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quotient = 32'hffffffff;
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remainder = numer_pipe_end;
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end
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else if (denom_pipe_end == 32'hffffffff && numer_pipe_end == 32'h80000000) begin
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// this edge case kills verilator in some cases by causing a division
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// overflow exception. INT_MIN / -1 (on x86)
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quotient = 0;
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remainder = 0;
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end
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else begin
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quotient = $signed($signed(numer_pipe_end)/$signed(denom_pipe_end));
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remainder = $signed($signed(numer_pipe_end)%$signed(denom_pipe_end));
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end
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end
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end
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else begin
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assign quotient = (denom_pipe_end == 0) ? 32'hffffffff : numer_pipe_end/denom_pipe_end;
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assign remainder = (denom_pipe_end == 0) ? numer_pipe_end : numer_pipe_end%denom_pipe_end;
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end
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end
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endgenerate
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endmodule : VX_divide
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125
hw/rtl/compat/VX_mult.v
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125
hw/rtl/compat/VX_mult.v
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@@ -0,0 +1,125 @@
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module VX_mult
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#(
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parameter WIDTHA=1,
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parameter WIDTHB=1,
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parameter WIDTHP=1,
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parameter REP="UNSIGNED",
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parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
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parameter PIPELINE=0,
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parameter FORCE_LE="NO"
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)
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(
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input clock, aclr, clken,
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input [WIDTHA-1:0] dataa,
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input [WIDTHB-1:0] datab,
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output reg [WIDTHP-1:0] result
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);
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// synthesis read_comments_as_HDL on
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// localparam IMPL = "quartus";
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// synthesis read_comments_as_HDL off
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// altera translate_off
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localparam IMPL="fallback";
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// altera translate_on
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generate
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if (IMPL == "quartus") begin
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localparam lpm_speed=SPEED == "HIGHEST" ? 10:5;
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if (FORCE_LE == "YES") begin
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lpm_mult#(
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.LPM_WIDTHA(WIDTHA),
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.LPM_WIDTHB(WIDTHB),
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.LPM_WIDTHP(WIDTHP),
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.LPM_REPRESENTATION(REP),
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.LPM_PIPELINE(PIPELINE),
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.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
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.MAXIMIZE_SPEED(lpm_speed)
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) quartus_mult(
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.clock(clock),
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.aclr(aclr),
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.clken(clken),
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.dataa(dataa),
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.datab(datab),
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.result(result)
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);
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end
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else begin
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lpm_mult#(
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.LPM_WIDTHA(WIDTHA),
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.LPM_WIDTHB(WIDTHB),
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.LPM_WIDTHP(WIDTHP),
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.LPM_REPRESENTATION(REP),
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.LPM_PIPELINE(PIPELINE),
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.MAXIMIZE_SPEED(lpm_speed)
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) quartus_mult(
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.clock(clock),
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.aclr(aclr),
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.clken(clken),
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.dataa(dataa),
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.datab(datab),
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.result(result)
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);
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end
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end
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else begin
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wire [WIDTHA-1:0] dataa_pipe_end;
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wire [WIDTHB-1:0] datab_pipe_end;
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if (PIPELINE == 0) begin
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assign dataa_pipe_end = dataa;
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assign datab_pipe_end = datab;
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end else begin
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reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
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reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
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genvar pipe_stage;
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for (pipe_stage = 0; pipe_stage < PIPELINE-1; pipe_stage = pipe_stage+1) begin : pipe_stages
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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dataa_pipe[pipe_stage+1] <= 0;
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datab_pipe[pipe_stage+1] <= 0;
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end
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else if (clken) begin
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dataa_pipe[pipe_stage+1] <= dataa_pipe[pipe_stage];
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datab_pipe[pipe_stage+1] <= datab_pipe[pipe_stage];
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end
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end
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end
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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dataa_pipe[0] <= 0;
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datab_pipe[0] <= 0;
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end
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else if (clken) begin
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dataa_pipe[0] <= dataa;
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datab_pipe[0] <= datab;
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end
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end
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assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
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assign datab_pipe_end = datab_pipe[PIPELINE-1];
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end
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/* * * * * * * * * * * * * * * * * * * * * * */
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/* Do the actual fallback computation here */
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/* * * * * * * * * * * * * * * * * * * * * * */
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if (REP == "SIGNED") begin
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assign result = $signed($signed(dataa_pipe_end)*$signed(datab_pipe_end));
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end
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else begin
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assign result = dataa_pipe_end*datab_pipe_end;
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end
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end
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endgenerate
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endmodule: VX_mult
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160
hw/rtl/compat/VX_tb_divide.sv
Normal file
160
hw/rtl/compat/VX_tb_divide.sv
Normal file
@@ -0,0 +1,160 @@
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`timescale 1ns/1ps
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module VX_tb_divide();
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`ifdef TRACE
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initial
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begin
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$dumpfile("trace.vcd");
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$dumpvars(0,test);
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end
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`endif
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reg clk;
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reg rst;
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reg [31:0] numer, denom;
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wire [31:0] o_div[0:7], o_rem[0:7];
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genvar i;
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generate
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for (i = 0; i < 8; i = i+1) begin : div_loop
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VX_divide#(
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.WIDTHN(32),
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.WIDTHD(32),
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.PIPELINE(i)
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) div(
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.clock(clk),
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.aclr(rst),
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.clken(1'b1),
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.numer(numer),
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.denom(denom),
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.quotient(o_div[i]),
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.remainder(o_rem[i])
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);
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end
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endgenerate
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initial begin
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clk = 0; rst = 0;
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numer = 56;
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denom = 11;
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$display("56 / 11 #0");
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if (o_div[0] != 5 || o_rem[0] != 1) begin
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$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[1] != 1'bx || o_rem[1] != 1'bx) begin
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$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
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$display("expected x,x EXITING");
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$finish();
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end
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if (o_div[2] != 1'bx || o_rem[2] != 1'bx) begin
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$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
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$display("expected x,x EXITING");
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$finish();
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end
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if (o_div[3] != 1'bx || o_rem[3] != 1'bx) begin
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$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
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$display("expected x,x EXITING");
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$finish();
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end
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#2;
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$display("56 / 11 #2");
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if (o_div[0] != 5 || o_rem[0] != 1) begin
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$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
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$display("expected 5,1, EXITING");
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$finish();
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end
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if (o_div[1] != 5 || o_rem[1] != 1) begin
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$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[2] != 1'bx || o_rem[2] != 1'bx) begin
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$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
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$display("expected x,x EXITING");
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$finish();
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end
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if (o_div[3] != 1'bx || o_rem[3] != 1'bx) begin
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$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
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$display("expected x,x EXITING");
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$finish();
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end
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#2;
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$display("56 / 11 #4");
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if (o_div[0] != 5 || o_rem[0] != 1) begin
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$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[1] != 5 || o_rem[1] != 1) begin
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$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[2] != 5 || o_rem[2] != 1) begin
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$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[3] != 1'bx || o_rem[3] != 1'bx) begin
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$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
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$display("expected x,x EXITING");
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$finish();
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end
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#2;
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$display("56 / 11 #6");
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if (o_div[0] != 5 || o_rem[0] != 1) begin
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$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[1] != 5 || o_rem[1] != 1) begin
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$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[2] != 5 || o_rem[2] != 1) begin
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$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[3] != 5 || o_rem[3] != 1) begin
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$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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$display("PASS");
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$finish();
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end
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always #1
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clk = ~clk;
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endmodule: VX_tb_divide
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Block a user