project directories reorganization
This commit is contained in:
Blaise Tine
433
hw/old_rtl/simulate/test_bench.h
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433
hw/old_rtl/simulate/test_bench.h
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// C++ libraries
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#include <utility>
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#include <iostream>
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#include <map>
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#include <iterator>
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#include <iomanip>
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#include <fstream>
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#include <unistd.h>
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#include <vector>
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#include <math.h>
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#include <algorithm>
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#include "VX_define.h"
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#include "ram.h"
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#include "VVortex.h"
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#include "verilated.h"
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#include "tb_debug.h"
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#ifdef VCD_OUTPUT
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#include <verilated_vcd_c.h>
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#endif
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unsigned long time_stamp = 0;
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double sc_time_stamp()
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{
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return time_stamp / 1000.0;
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}
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class Vortex
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{
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public:
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Vortex();
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~Vortex();
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bool simulate(std::string);
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private:
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void ProcessFile(void);
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void print_stats(bool = true);
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bool ibus_driver();
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bool dbus_driver();
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void io_handler();
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RAM ram;
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VVortex * vortex;
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unsigned start_pc;
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bool refill_d;
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unsigned refill_addr_d;
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bool refill_i;
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unsigned refill_addr_i;
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long int curr_cycle;
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bool stop;
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bool unit_test;
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std::string instruction_file_name;
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std::ofstream results;
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int stats_static_inst;
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int stats_dynamic_inst;
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int stats_total_cycles;
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int stats_fwd_stalls;
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int stats_branch_stalls;
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int debug_state;
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int ibus_state;
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int dbus_state;
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int debug_return;
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int debug_wait_num;
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int debug_inst_num;
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int debug_end_wait;
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int debug_debugAddr;
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double stats_sim_time;
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#ifdef VCD_OUTPUT
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VerilatedVcdC *m_trace;
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#endif
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};
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Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
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stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
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debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
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debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
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{
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this->vortex = new VVortex;
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#ifdef VCD_OUTPUT
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this->m_trace = new VerilatedVcdC;
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this->vortex->trace(m_trace, 99);
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this->m_trace->open("trace.vcd");
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#endif
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this->results.open("../results.txt");
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}
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Vortex::~Vortex()
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{
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#ifdef VCD_OUTPUT
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m_trace->close();
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#endif
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this->results.close();
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delete this->vortex;
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}
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void Vortex::ProcessFile(void)
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{
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loadHexImpl(this->instruction_file_name.c_str(), &this->ram);
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}
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void Vortex::print_stats(bool cycle_test)
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{
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if (cycle_test)
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{
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this->results << std::left;
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// this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
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this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
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this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
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this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
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this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
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this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl;
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this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
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}
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else
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{
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this->results << std::left;
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this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
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this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
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}
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uint32_t status;
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ram.getWord(0, &status);
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if (this->unit_test)
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{
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if (status == 1)
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{
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this->results << std::setw(24) << "# GRADE:" << "PASSING\n";
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} else
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{
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this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n";
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}
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}
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else
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{
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this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n";
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}
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this->stats_static_inst = 0;
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this->stats_dynamic_inst = -1;
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this->stats_total_cycles = 0;
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this->stats_fwd_stalls = 0;
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this->stats_branch_stalls = 0;
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}
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bool Vortex::ibus_driver()
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{
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vortex->i_m_ready_i = false;
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{
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// int dcache_num_words_per_block
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if (refill_i)
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{
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refill_i = false;
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vortex->i_m_ready_i = true;
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for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++)
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{
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for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++)
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{
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unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank;
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unsigned curr_addr = refill_addr_i + (4*curr_index);
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unsigned curr_value;
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ram.getWord(curr_addr, &curr_value);
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vortex->i_m_readdata_i[curr_bank][curr_word] = curr_value;
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}
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}
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}
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else
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{
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if (vortex->o_m_valid_i)
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{
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if (vortex->o_m_read_or_write_i)
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{
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// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
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unsigned base_addr = vortex->o_m_evict_addr_i;
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for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++)
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{
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for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++)
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{
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unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank;
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unsigned curr_addr = base_addr + (4*curr_index);
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unsigned curr_value = vortex->o_m_writedata_i[curr_bank][curr_word];
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ram.writeWord( curr_addr, &curr_value);
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}
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}
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}
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// Respond next cycle
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refill_i = true;
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refill_addr_i = vortex->o_m_read_addr_i;
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}
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}
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}
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return false;
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}
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void Vortex::io_handler()
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{
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if (vortex->io_valid)
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{
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uint32_t data_write = (uint32_t) vortex->io_data;
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char c = (char) data_write;
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std::cerr << c;
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// std::cout << c;
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}
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}
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bool Vortex::dbus_driver()
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{
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vortex->i_m_ready_d = false;
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{
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// int dcache_num_words_per_block
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if (refill_d)
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{
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refill_d = false;
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vortex->i_m_ready_d = true;
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for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++)
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{
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for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++)
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{
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unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank;
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unsigned curr_addr = refill_addr_d + (4*curr_index);
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unsigned curr_value;
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ram.getWord(curr_addr, &curr_value);
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vortex->i_m_readdata_d[curr_bank][curr_word] = curr_value;
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}
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}
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}
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else
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{
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if (vortex->o_m_valid_d)
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{
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if (vortex->o_m_read_or_write_d)
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{
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// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
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unsigned base_addr = vortex->o_m_evict_addr_d;
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for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++)
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{
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for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++)
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{
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unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank;
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unsigned curr_addr = base_addr + (4*curr_index);
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unsigned curr_value = vortex->o_m_writedata_d[curr_bank][curr_word];
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ram.writeWord( curr_addr, &curr_value);
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}
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}
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}
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// Respond next cycle
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refill_d = true;
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refill_addr_d = vortex->o_m_read_addr_d;
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}
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}
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}
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return false;
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}
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bool Vortex::simulate(std::string file_to_simulate)
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{
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this->instruction_file_name = file_to_simulate;
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// this->results << "\n****************\t" << file_to_simulate << "\t****************\n";
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this->ProcessFile();
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// auto start_time = std::chrono::high_resolution_clock::now();
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static bool stop = false;
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static int counter = 0;
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counter = 0;
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stop = false;
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// auto start_time = clock();
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// vortex->reset = 1;
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// vortex->reset = 0;
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unsigned curr_inst;
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unsigned new_PC;
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// while (this->stop && (!(stop && (counter > 5))))
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// {
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// // std::cout << "************* Cycle: " << cycle << "\n";
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// bool istop = ibus_driver();
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// bool dstop = !dbus_driver();
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// vortex->clk = 1;
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// vortex->eval();
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// vortex->clk = 0;
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// vortex->eval();
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// stop = istop && dstop;
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// if (stop)
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// {
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// counter++;
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// } else
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// {
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// counter = 0;
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// }
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// cycle++;
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// }
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bool istop;
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bool dstop;
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bool cont = false;
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// for (int i = 0; i < 500; i++)
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vortex->reset = 1;
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vortex->clk = 0;
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vortex->eval();
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// m_trace->dump(10);
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vortex->reset = 1;
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vortex->clk = 1;
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vortex->eval();
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// m_trace->dump(11);
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vortex->reset = 0;
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vortex->clk = 0;
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// unsigned cycles;
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counter = 0;
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this->stats_total_cycles = 12;
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while (this->stop && ((counter < 5)))
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// while (this->stats_total_cycles < 10)
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{
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// printf("-------------------------\n");
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// std::cout << "Counter: " << counter << "\n";
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// if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
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// dstop = !dbus_driver();
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#ifdef VCD_OUTPUT
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m_trace->dump(2*this->stats_total_cycles);
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#endif
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vortex->clk = 1;
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vortex->eval();
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istop = ibus_driver();
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dstop = !dbus_driver();
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io_handler();
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#ifdef VCD_OUTPUT
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m_trace->dump((2*this->stats_total_cycles)+1);
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#endif
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vortex->clk = 0;
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vortex->eval();
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// stop = istop && dstop;
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stop = vortex->out_ebreak;
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if (stop || cont)
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// if (istop)
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{
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cont = true;
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counter++;
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} else
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{
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counter = 0;
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}
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++time_stamp;
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++stats_total_cycles;
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}
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std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
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int status = (unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf;
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// std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n";
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// std::cout << "Something: " << result << '\n';
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// uint32_t status;
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// ram.getWord(0, &status);
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this->print_stats();
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return (status == 1);
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// return (1 == 1);
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}
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