project directories reorganization
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Blaise Tine
233
hw/old_rtl/cache/cache_set.v
vendored
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233
hw/old_rtl/cache/cache_set.v
vendored
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// To Do: Change way_id_out to an internal register which holds when in between access and finished.
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// Also add a bit about wheter the "Way ID" is valid / being held or if it is just default
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// Also make sure all possible output states are transmitted back to the bank correctly
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// `include "VX_define.v"
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module cache_set(clk,
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rst,
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// These next 4 are possible modes that the Set could be in, I am making them 4 different variables for indexing purposes
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access, // First
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find_evict,
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write_from_mem,
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idle,
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// entry,
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o_tag,
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writedata,
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//byte_en,
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write,
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//word_en,
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//way_id_in,
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//way_id_out,
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readdata,
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//wb_addr,
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hit,
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eviction_wb,
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eviction_tag,
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//eviction_data,
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//modify,
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miss
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//valid_data
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//read_miss
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);
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parameter cache_entry = 14;
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parameter ways_per_set = 4;
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input wire clk, rst;
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input wire access;
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input wire find_evict;
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input wire write_from_mem;
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input wire idle;
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//input wire [cache_entry-1:0] entry;
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input wire [1:0] o_tag;
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input wire [31:0] writedata;
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//input wire [3:0] byte_en;
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input wire write; // 0 == False
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//input wire [3:0] word_en;
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//input wire read_miss;
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//input wire [1:0] way_id_in;
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//output reg [1:0] way_id_out;
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output reg [31:0] readdata;
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//output reg [3:0] hit;
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output reg hit;
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output reg miss;
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output wire eviction_wb;
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output wire [1:0] eviction_tag;
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reg [31:0] eviction_data;
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//output wire [22:0] wb_addr;
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//output wire modify, valid_data;
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//wire [2:0] i_tag;
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//wire dirty;
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//wire [24-cache_entry:0] write_tag_data;
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// Table for one set
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reg [2:0] counter; // Determines which to evict
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reg valid [ways_per_set-1:0];
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reg [1:0] tag [ways_per_set-1:0];
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reg clean [ways_per_set-1:0];
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reg [31:0] data [ways_per_set-1:0];
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assign eviction_wb = miss && clean[counter[1:0]] != 1'b1 && valid[counter[1:0]] == 1'b1;
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assign eviction_tag = tag[counter[1:0]];
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//assign eviction_data = data[counter[1:0]];
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//assign hit = valid_data && (o_tag == i_tag);
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//assign modify = valid_data && (o_tag != i_tag) && dirty;
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//assign miss = !valid_data || ((o_tag != i_tag) && !dirty);
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//assign wb_addr = {i_tag, entry};
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always @(posedge clk) begin
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if (rst) begin
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end
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if (find_evict) begin
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if (tag[0] == o_tag && valid[0]) begin
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readdata <= data[0];
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end else if (tag[1] == o_tag && valid[1]) begin
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readdata <= data[1];
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end else if (tag[2] == o_tag && valid[2]) begin
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readdata <= data[2];
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end else if (tag[3] == o_tag && valid[3]) begin
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readdata <= data[3];
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end
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end else if (access) begin
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//tag[`NT_M1:0] <= i_p_addr[`NT_M1:0][13:12];
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counter <= ((counter + 1) ^ 3'b100); // Counter determining which to evict in the event of miss only increment when miss !!! NEED TO FIX LOGIC
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// Hit in First Column
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if (tag[0] == o_tag && valid[0]) begin
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if (write == 1'b0) begin // if it is a read
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if (clean[0] == 1'b1 ) begin
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//hit <= 4'b0001;
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hit <= 1'b1;
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readdata <= data[0];
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miss <= 1'b0;
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end else begin
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//hit <= 4'b0000; // SHOULD PROBABLY TRACK WHERE THIS MISS IS IN A DIFFERENT VARIABLE
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hit <= 1'b0;
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readdata <= 32'b0;
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miss <= 1'b1;
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end
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end else if (write == 1'b1) begin
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data[0] <= writedata;
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clean[0] <= 1'b0;
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//hit <= 4'b0001;
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hit <= 1'b1;
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end
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end
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// Hit in Second Column
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else if (tag[1] == o_tag && valid[1]) begin
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if (write == 1'b0) begin // if it is a read
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if (clean[1] == 1'b1 ) begin
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//hit <= 4'b0010;
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hit <= 1'b1;
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readdata <= data[1];
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miss <= 1'b0;
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end else begin
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//hit <= 4'b0000;
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hit <= 1'b0;
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readdata <= 32'b0;
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miss <= 1'b1;
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end
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end else if (write == 1'b1) begin
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data[1] <= writedata;
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clean[1] <= 1'b0;
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//hit <= 4'b0010;
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hit <= 1'b1;
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end
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end
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// Hit in Third Column
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else if (tag[2] == o_tag && valid[2]) begin
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if (write == 1'b0) begin // if it is a read
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if (clean[2] == 1'b1 ) begin
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//hit <= 4'b0100;
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hit <= 1'b1;
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readdata <= data[2];
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miss <= 1'b0;
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end else begin
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//hit <= 4'b0000;
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hit <= 1'b0;
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readdata <= 32'b0;
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miss <= 1'b1;
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end
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end else if (write == 1'b1) begin
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data[2] <= writedata;
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clean[2] <= 1'b0;
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//hit <= 4'b0100;
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hit <= 1'b1;
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end
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end
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// Hit in Fourth Column
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else if (tag[3] == o_tag && valid[3]) begin
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if (write == 1'b0) begin // if it is a read
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if (clean[3] == 1'b1 ) begin
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//hit <= 4'b1000;
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hit <= 1'b1;
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readdata <= data[3];
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miss <= 1'b0;
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end else begin
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//hit <= 4'b0000;
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hit <= 1'b0;
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readdata <= 32'b0;
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miss <= 1'b1;
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end
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end else if (write == 1'b1) begin
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data[3] <= writedata;
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clean[3] <= 1'b0;
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//hit <= 4'b1000;
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hit <= 1'b1;
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end
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end
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// Miss
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else begin
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//way_id_out <= counter;
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miss <= 1'b1;
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if (write == 1'b0) begin // Read Miss
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clean[counter[1:0]] <= 1'b1;
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data[counter[1:0]] <= 32'h7FF; // FIX WITH ACTUAL MEMORY ACCESS
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end else if (write == 1'b1) begin // Write Miss
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clean[counter[1:0]] <= 1'b1;
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data[counter[1:0]] <= writedata;
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end
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end
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end
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if (write_from_mem) begin
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tag[counter[1:0]] <= o_tag;
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valid[counter[1:0]] <= 1'b1;
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hit <= 1'b1;
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if (write == 1'b0) begin // Read Miss
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clean[counter[1:0]] <= 1'b1;
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data[counter[1:0]] <= 32'h7FF; // FIX WITH ACTUAL MEMORY ACCESS
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end else if (write == 1'b1) begin // Write Miss
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clean[counter[1:0]] <= 1'b0;
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data[counter[1:0]] <= writedata;
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end
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end
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if (idle) begin // Set "way" register equal to invalid value
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hit <= 1'b1; // set to know it is ready
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miss <= 1'b0;
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readdata <= 32'hFFFFFFFF;
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end
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if (find_evict) begin // Keep "way" value the same !!!! Fix. Need to send back data with matching tag. Also need to ensure evicted data doesnt get lost
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if (tag[3] == o_tag && valid[3]) begin
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readdata <= data[3];
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end else if (tag[1] == o_tag && valid[1]) begin
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readdata <= data[1];
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end else if (tag[2] == o_tag && valid[2]) begin
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readdata <= data[2];
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end else if (tag[0] == o_tag && valid[0]) begin
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readdata <= data[0];
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end else begin
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readdata <= eviction_data;
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end
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hit <= 1'b1;
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miss <= 1'b0;
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end
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counter <= ((counter + 1) ^ 3'b100); // Counter determining which to evict in the event of miss only increment when miss !!! NEED TO FIX LOGIC
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eviction_data <= data[counter[1:0]];
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end
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endmodule
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