Started simX
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felsabbagh3
286
simX/core.cpp
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286
simX/core.cpp
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/*******************************************************************************
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HARPtools by Chad D. Kersey, Summer 2011
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*******************************************************************************/
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#include <iostream>
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#include <iomanip>
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// #define USE_DEBUG 7
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// #define PRINT_ACTIVE_THREADS
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#include "include/types.h"
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#include "include/util.h"
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#include "include/archdef.h"
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#include "include/mem.h"
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#include "include/enc.h"
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#include "include/core.h"
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#include "include/debug.h"
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#ifdef EMU_INSTRUMENTATION
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#include "include/qsim-harp.h"
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#endif
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using namespace Harp;
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using namespace std;
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#ifdef EMU_INSTRUMENTATION
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void Harp::reg_doRead(Word cpuId, Word regNum) {
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Harp::OSDomain::osDomain->do_reg(cpuId, regNum, 8, true);
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}
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void Harp::reg_doWrite(Word cpuId, Word regNum) {
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Harp::OSDomain::osDomain->do_reg(cpuId, regNum, 8, false);
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}
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#endif
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Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id):
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a(a), iDec(d), mem(mem), steps(0)
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{
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cache_simulator = new Vcache_simX;
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for (unsigned i = 0; i < a.getNWarps(); ++i)
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w.push_back(Warp(this, i));
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w[0].activeThreads = 1;
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w[0].spawned = true;
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}
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bool Core::interrupt(Word r0) {
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w[0].interrupt(r0);
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}
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void Core::step()
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{
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this->fetch();
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}
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void Core::fetch()
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{
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++steps;
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#ifdef PRINT_ACTIVE_THREADS
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cout << endl << "Threads:";
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#endif
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for (unsigned i = 0; i < w.size(); ++i) {
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if (w[i].activeThreads) {
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trace_inst_t trace_inst;
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trace_inst.valid_inst = false;
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trace_inst.pc = 0;
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trace_inst.wid = i;
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trace_inst.rs1 = -1;
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trace_inst.rs2 = -1;
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trace_inst.rd = -1;
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trace_inst.is_lw = false;
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trace_inst.is_sw = false;
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trace_inst.mem_addresses = new unsigned[a.getNThds()];
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trace_inst.mem_stall_cycles = 0;
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trace_inst.fetch_stall_cycles = 0;
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trace_inst.stall_warp = false;
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D(3, "Core step stepping warp " << i << '[' << w[i].activeThreads << ']');
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w[i].step(&trace_inst);
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D(3, "Now " << w[i].activeThreads << " active threads in " << i);
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D(-1, "********************************");
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D(-1, "*** valid: " << trace_inst.valid_inst << " pc: " << hex << trace_inst.pc << dec << " rs1..rs2..rd " << trace_inst.rs1 << ".." << trace_inst.rs2 << ".." << trace_inst.rd << "\n");
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D(-1, "********************************");
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}
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#ifdef PRINT_ACTIVE_THREADS
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for (unsigned j = 0; j < w[i].tmask.size(); ++j) {
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if (w[i].activeThreads > j && w[i].tmask[j]) cout << " 1";
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else cout << " 0";
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if (j != w[i].tmask.size()-1 || i != w.size()-1) cout << ',';
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}
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#endif
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}
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#ifdef PRINT_ACTIVE_THREADS
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cout << endl;
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#endif
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}
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void Core::decode()
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{
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}
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void Core::scheduler()
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{
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}
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void Core::gpr_read()
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{
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}
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void Core::execute_unit()
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{
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}
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void Core::load_store()
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{
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}
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bool Core::running() const {
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for (unsigned i = 0; i < w.size(); ++i)
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if (w[i].running()) return true;
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return false;
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}
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void Core::printStats() const {
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unsigned long insts = 0;
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for (unsigned i = 0; i < w.size(); ++i)
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insts += w[i].insts;
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cout << "Total steps: " << steps << endl;
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cout << "Total insts: " << insts << endl;
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for (unsigned i = 0; i < w.size(); ++i) {
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cout << "=== Warp " << i << " ===" << endl;
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w[i].printStats();
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}
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}
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Warp::Warp(Core *c, Word id) :
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core(c), pc(0x80000000), interruptEnable(true),
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supervisorMode(true), activeThreads(0), reg(0), pred(0),
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shadowReg(core->a.getNRegs()), shadowPReg(core->a.getNPRegs()), id(id),
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spawned(false), steps(0), insts(0), loads(0), stores(0)
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{
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D(3, "Creating a new thread with PC: " << hex << this->pc << '\n');
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/* Build the register file. */
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Word regNum(0);
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for (Word j = 0; j < core->a.getNThds(); ++j) {
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reg.push_back(vector<Reg<Word> >(0));
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for (Word i = 0; i < core->a.getNRegs(); ++i) {
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reg[j].push_back(Reg<Word>(id, regNum++));
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}
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pred.push_back(vector<Reg<bool> >(0));
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for (Word i = 0; i < core->a.getNPRegs(); ++i) {
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pred[j].push_back(Reg<bool>(id, regNum++));
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}
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bool act = false;
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if (j == 0) act = true;
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tmask.push_back(act);
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shadowTmask.push_back(act);
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}
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Word csrNum(0);
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for (Word i = 0; i < (1<<12); i++)
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{
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csr.push_back(Reg<uint16_t>(id, regNum++));
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}
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/* Set initial register contents. */
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reg[0][0] = (core->a.getNThds()<<(core->a.getWordSize()*8 / 2)) | id;
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}
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void Warp::step(trace_inst_t * trace_inst) {
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Size fetchPos(0), decPos, wordSize(core->a.getWordSize());
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vector<Byte> fetchBuffer(wordSize);
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if (activeThreads == 0) return;
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++steps;
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D(3, "in step pc=0x" << hex << pc);
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// std::cout << "pc: " << hex << pc << "\n";
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trace_inst->pc = pc;
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/* Fetch and decode. */
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if (wordSize < sizeof(pc)) pc &= ((1ll<<(wordSize*8))-1);
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Instruction *inst;
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bool fetchMore;
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fetchMore = false;
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unsigned fetchSize(wordSize - (pc+fetchPos)%wordSize);
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fetchBuffer.resize(fetchPos + fetchSize);
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Word fetched = core->mem.fetch(pc + fetchPos, supervisorMode);
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writeWord(fetchBuffer, fetchPos, fetchSize, fetched);
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decPos = 0;
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inst = core->iDec.decode(fetchBuffer, decPos, trace_inst);
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D(3, "Fetched at 0x" << hex << pc);
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D(3, "0x" << hex << pc << ": " << *inst);
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// Update pc
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pc += decPos;
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// Execute
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inst->executeOn(*this);
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// At Debug Level 3, print debug info after each instruction.
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#ifdef USE_DEBUG
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if (USE_DEBUG >= 3) {
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D(3, "Register state:");
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for (unsigned i = 0; i < reg[0].size(); ++i) {
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D_RAW(" %r" << setfill(' ') << setw(2) << dec << i << ':');
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for (unsigned j = 0; j < reg.size(); ++j)
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D_RAW(' ' << setfill('0') << setw(8) << hex << reg[j][i] << setfill(' ') << ' ');
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D_RAW('(' << shadowReg[i] << ')' << endl);
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}
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D(3, "Thread mask:");
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D_RAW(" ");
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for (unsigned i = 0; i < tmask.size(); ++i) D_RAW(tmask[i] << ' ');
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D_RAW(endl);
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D_RAW(endl);
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D_RAW(endl);
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}
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#endif
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// Clean up.
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delete inst;
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}
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bool Warp::interrupt(Word r0) {
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if (!interruptEnable) return false;
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#ifdef EMU_INSTRUMENTATION
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Harp::OSDomain::osDomain->do_int(0, r0);
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#endif
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shadowActiveThreads = activeThreads;
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shadowTmask = tmask;
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shadowInterruptEnable = interruptEnable; /* For traps. */
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shadowSupervisorMode = supervisorMode;
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for (Word i = 0; i < reg[0].size(); ++i) shadowReg[i] = reg[0][i];
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for (Word i = 0; i < pred[0].size(); ++i) shadowPReg[i] = pred[0][i];
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for (Word i = 0; i < reg.size(); ++i) tmask[i] = 1;
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shadowPc = pc;
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activeThreads = 1;
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interruptEnable = false;
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supervisorMode = true;
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reg[0][0] = r0;
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pc = core->interruptEntry;
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return true;
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}
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void Warp::printStats() const {
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cerr << "Steps : " << steps << endl
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<< "Insts : " << insts << endl
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<< "Loads : " << loads << endl
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<< "Stores: " << stores << endl;
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unsigned const grade = reg[0][28];
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if (grade == 1) cerr << "GRADE: PASSED\n";
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else cerr << "GRADE: FAILED " << (grade >> 1) << "\n";
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}
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