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Finalized GPR with 3-Port Structure

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This commit is contained in:
felsabbagh3
2019-09-11 14:53:32 -04:00
parent 1b25b10644
commit fb3bc60189
13 changed files with 1440 additions and 4192 deletions
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60
rtl/VX_gpr.v
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@@ -14,32 +14,50 @@ module VX_gpr (
wire write_enable;
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
// USING RAM blocks
// First RAM
byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable),
.clk (clk),
.waddr(VX_writeback_inter.rd),
.raddr(VX_gpr_read.rs1),
.be (VX_writeback_inter.wb_valid),
.wdata(VX_writeback_inter.write_data),
.q (out_a_reg_data)
);
byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable),
.clk (clk),
.waddr (VX_writeback_inter.rd),
.raddr1(VX_gpr_read.rs1),
.raddr2(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata (VX_writeback_inter.write_data),
.q1 (out_a_reg_data),
.q2 (out_b_reg_data)
);
// Second RAM block
byte_enabled_simple_dual_port_ram second_ram(
.we (write_enable),
.clk (clk),
.waddr(VX_writeback_inter.rd),
.raddr(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata(VX_writeback_inter.write_data),
.q (out_b_reg_data)
);
// // USING RAM blocks
// // First RAM
// byte_enabled_simple_dual_port_ram first_ram(
// .we (write_enable),
// .clk (clk),
// .waddr(VX_writeback_inter.rd),
// .raddr(VX_gpr_read.rs1),
// .be (VX_writeback_inter.wb_valid),
// .wdata(VX_writeback_inter.write_data),
// .q (out_a_reg_data)
// );
// // Second RAM block
// byte_enabled_simple_dual_port_ram second_ram(
// .we (write_enable),
// .clk (clk),
// .waddr(VX_writeback_inter.rd),
// .raddr(VX_gpr_read.rs2),
// .be (VX_writeback_inter.wb_valid),
// .wdata(VX_writeback_inter.write_data),
// .q (out_b_reg_data)
// );
// logic[`NT_M1:0][31:0] gpr[31:0]; // gpr[register_number][thread_number][data_bits]
// wire write_enable;