From faf5fe3838b28ba85cc1dac4d79fdca0c8334a46 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 17 Nov 2023 19:08:32 -0800 Subject: [PATCH] Assert ready when write response is coming back Since the core's response ready signal depends on response valid, but core does not accept write ACKs, we need to manually assert ready when there is a valid response coming in for a write regardless of the core's ready state (which would be 0). --- hw/rtl/VX_core_wrapper.sv | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/rtl/VX_core_wrapper.sv b/hw/rtl/VX_core_wrapper.sv index 4ba45bfa..d15631b7 100644 --- a/hw/rtl/VX_core_wrapper.sv +++ b/hw/rtl/VX_core_wrapper.sv @@ -268,10 +268,12 @@ module Vortex import VX_gpu_pkg::*; #( assign dcache_bus_if[2].rsp_data.tag = dmem_2_d_bits_source; assign dcache_bus_if[3].rsp_data.tag = dmem_3_d_bits_source; - assign dmem_0_d_ready = dcache_bus_if[0].rsp_ready; - assign dmem_1_d_ready = dcache_bus_if[1].rsp_ready; - assign dmem_2_d_ready = dcache_bus_if[2].rsp_ready; - assign dmem_3_d_ready = dcache_bus_if[3].rsp_ready; + // When there's a write ACK coming back, ready bit should always be 1 to + // accept them because core does not accept them on their own + assign dmem_0_d_ready = dcache_bus_if[0].rsp_ready || (dmem_0_d_bits_opcode == 3'd0 /*AccessAck*/); + assign dmem_1_d_ready = dcache_bus_if[1].rsp_ready || (dmem_1_d_bits_opcode == 3'd0 /*AccessAck*/); + assign dmem_2_d_ready = dcache_bus_if[2].rsp_ready || (dmem_2_d_bits_opcode == 3'd0 /*AccessAck*/); + assign dmem_3_d_ready = dcache_bus_if[3].rsp_ready || (dmem_3_d_bits_opcode == 3'd0 /*AccessAck*/); assign dmem_0_a_valid = dcache_bus_if[0].req_valid; assign dmem_1_a_valid = dcache_bus_if[1].req_valid;