diff --git a/hw/rtl/tex_unit/VX_tex_bilerp.v b/hw/rtl/tex_unit/VX_tex_bilerp.v deleted file mode 100644 index 0388dbfe..00000000 --- a/hw/rtl/tex_unit/VX_tex_bilerp.v +++ /dev/null @@ -1,68 +0,0 @@ -`include "VX_tex_define.vh" - -module VX_tex_bilerp #( - parameter CORE_ID = 0 -) ( - input wire [`BLEND_FRAC_64-1:0] blendU, - input wire [`BLEND_FRAC_64-1:0] blendV, - - input wire [3:0][63:0] texels, - input wire [`NUM_COLOR_CHANNEL-1:0] color_enable, - - output wire [31:0] sampled_data -); - `UNUSED_PARAM (CORE_ID) - - wire [63:0] UL_lerp; - wire [63:0] UH_lerp; - wire [63:0] V_lerp; - reg [31:0] sampled_r; - - VX_tex_lerp #( - ) tex_lerp_UL ( - .blend(blendU), - .in_texels({texels[1], texels[0]}), - .lerp_texel(UL_lerp) - ); - - VX_tex_lerp #( - ) tex_lerp_UH ( - .blend(blendU), - .in_texels({texels[3], texels[2]}), - .lerp_texel(UH_lerp) - ); - - VX_tex_lerp #( - ) tex_lerp_V ( - .blend(blendV), - .in_texels({UH_lerp, UL_lerp}), - .lerp_texel(V_lerp) - ); - - `UNUSED_VAR (V_lerp[63:56]) - - always @(*) begin - if (color_enable[3]==1'b1) //R - sampled_r[31:24] = V_lerp[55:48]; - else - sampled_r[31:24] = {`TEX_COLOR_BITS{1'b0}}; - - if (color_enable[2]==1'b1) //G - sampled_r[23:16] = V_lerp[39:32]; - else - sampled_r[23:16] = {`TEX_COLOR_BITS{1'b0}}; - - if (color_enable[1]==1'b1) //B - sampled_r[15:8] = V_lerp[23:16]; - else - sampled_r[15:8] = {`TEX_COLOR_BITS{1'b0}}; - - if (color_enable[0]==1'b1) //A - sampled_r[7:0] = V_lerp[7:0]; - else - sampled_r[7:0] = {`TEX_COLOR_BITS{1'b1}}; - end - - assign sampled_data = sampled_r; - -endmodule \ No newline at end of file diff --git a/hw/rtl/tex_unit/VX_tex_define.vh b/hw/rtl/tex_unit/VX_tex_define.vh index 4ba00a75..380ee659 100644 --- a/hw/rtl/tex_unit/VX_tex_define.vh +++ b/hw/rtl/tex_unit/VX_tex_define.vh @@ -11,10 +11,6 @@ `define CLAMP(x,lo,hi) (($signed(x) < $signed(lo)) ? lo : ((x > hi) ? hi : x)) -`define BLEND_FRAC_64 8 - -`define LERP_64(x1,x2,frac) ((x2 + (((x1 - x2) * frac) >> `BLEND_FRAC_64)) & 64'h00ff00ff00ff00ff) - `define TEX_ADDR_BITS 32 `define TEX_FORMAT_BITS 3 `define TEX_WRAP_BITS 2 @@ -32,10 +28,8 @@ `define TEX_WRAP_REPEAT 1 `define TEX_WRAP_MIRROR 2 -`define MAX_COLOR_WIDTH 8 -`define NUM_COLOR_CHANNEL 4 - `define TEX_COLOR_BITS 8 +`define BLEND_FRAC 8 `define TEX_FORMAT_R8G8B8A8 `TEX_FORMAT_BITS'(0) `define TEX_FORMAT_R5G6B5 `TEX_FORMAT_BITS'(1) diff --git a/hw/rtl/tex_unit/VX_tex_format.v b/hw/rtl/tex_unit/VX_tex_format.v index af217f8a..33cb4d24 100644 --- a/hw/rtl/tex_unit/VX_tex_format.v +++ b/hw/rtl/tex_unit/VX_tex_format.v @@ -1,125 +1,57 @@ `include "VX_tex_define.vh" module VX_tex_format #( - parameter CORE_ID = 0, - parameter NUM_TEXELS = 4 //BILINEAR + parameter CORE_ID = 0 ) ( - input wire [NUM_TEXELS-1:0][31:0] texel_data, - input wire [`TEX_FORMAT_BITS-1:0] format, - - output wire [`NUM_COLOR_CHANNEL-1:0] color_enable, - output wire [NUM_TEXELS-1:0][63:0] formatted_lerp_texel, - output wire [31:0] formatted_pt_texel + input wire [`TEX_FORMAT_BITS-1:0] format, + input wire [31:0] texel_in, + output wire [31:0] texel_out ); `UNUSED_PARAM (CORE_ID) - reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r; - reg [NUM_TEXELS-1:0][63:0] formatted_texel_r; - reg [31:0] formatted_pt_r; + reg [31:0] texel_out_r; - always @(*) begin - // bilerp/trilerp input - for (integer i = 0; i> BLEND_FRAC_64 / >> 8 + assign in1_w[15:00] = {8'h00, in1[07:00]}; + assign in1_w[31:16] = {8'h00, in1[15:08]}; + assign in1_w[47:32] = {8'h00, in1[23:16]}; + assign in1_w[63:48] = {8'h00, in1[31:24]}; - assign lerp_i1 = (in_texels[0] - in_texels[1]) * blend; - assign lerp_i2 = in_texels[1] + {8'h00,lerp_i1[63:56], 8'h00,lerp_i1[47:40], 8'h00,lerp_i1[31:24], 8'h00,lerp_i1[15:8]}; - assign lerp_texel = lerp_i2 & 64'h00ff00ff00ff00ff; + assign in2_w[15:00] = {8'h00, in2[07:00]}; + assign in2_w[31:16] = {8'h00, in2[15:08]}; + assign in2_w[47:32] = {8'h00, in2[23:16]}; + assign in2_w[63:48] = {8'h00, in2[31:24]}; + + assign lerp1 = (in2_w - in1_w) * blend; + + assign lerp2 = in1_w + {8'h00,lerp1[63:56], 8'h00,lerp1[47:40], 8'h00,lerp1[31:24], 8'h00,lerp1[15:8]}; + + assign out[07:00] = lerp2[07:00]; + assign out[15:08] = lerp2[23:16]; + assign out[23:16] = lerp2[39:32]; + assign out[31:24] = lerp2[55:48]; endmodule \ No newline at end of file diff --git a/hw/rtl/tex_unit/VX_tex_memory.v b/hw/rtl/tex_unit/VX_tex_memory.v index 1bf041c4..a77293ac 100644 --- a/hw/rtl/tex_unit/VX_tex_memory.v +++ b/hw/rtl/tex_unit/VX_tex_memory.v @@ -278,7 +278,7 @@ module VX_tex_memory #( $time, CORE_ID, rsp_wid, rsp_PC, rsp_filter); `PRINT_ARRAY2D(rsp_data, 4, `NUM_THREADS); $write("\n"); - end + end end `endif diff --git a/hw/rtl/tex_unit/VX_tex_sampler.v b/hw/rtl/tex_unit/VX_tex_sampler.v index da3d8aac..d8cb2ff9 100644 --- a/hw/rtl/tex_unit/VX_tex_sampler.v +++ b/hw/rtl/tex_unit/VX_tex_sampler.v @@ -39,37 +39,47 @@ module VX_tex_sampler #( for (genvar i = 0; i < `NUM_THREADS; i++) begin - wire [31:0] req_data_bilerp; - wire [3:0][63:0] formatted_data; - wire [31:0] formatted_pt_data; - wire [`NUM_COLOR_CHANNEL-1:0] color_enable; + wire [3:0][31:0] fmt_texels; + wire [31:0] texel_ul, texel_uh, texel_v; - VX_tex_format #( - .CORE_ID (CORE_ID), - .NUM_TEXELS (4) - ) tex_format ( - .texel_data (req_texels[i]), - .format (req_format), + wire [`BLEND_FRAC-1:0] blend_u = req_u[i][`BLEND_FRAC-1:0]; + wire [`BLEND_FRAC-1:0] blend_v = req_v[i][`BLEND_FRAC-1:0]; - .color_enable (color_enable), - .formatted_lerp_texel(formatted_data), - .formatted_pt_texel(formatted_pt_data) + for (genvar j = 0; j < 4; j++) begin + VX_tex_format #( + .CORE_ID (CORE_ID) + ) tex_format ( + .format (req_format), + .texel_in (req_texels[i][j]), + .texel_out (fmt_texels[j]) + ); + end + + VX_tex_lerp #( + ) tex_lerp_ul ( + .blend (blend_u), + .in1 (fmt_texels[0]), + .in2 (fmt_texels[1]), + .out (texel_ul) ); - VX_tex_bilerp #( - .CORE_ID (CORE_ID) - ) tex_bilerp ( - .blendU (req_u[i][`BLEND_FRAC_64-1:0]), - .blendV (req_v[i][`BLEND_FRAC_64-1:0]), + VX_tex_lerp #( + ) tex_lerp_uh ( + .blend (blend_u), + .in1 (fmt_texels[2]), + .in2 (fmt_texels[3]), + .out (texel_uh) + ); - .color_enable (color_enable), - .texels (formatted_data), - - .sampled_data (req_data_bilerp) - ); - - assign req_data[i] = (req_filter == `TEX_FILTER_BITS'(0)) ? formatted_pt_data : req_data_bilerp; + VX_tex_lerp #( + ) tex_lerp_v ( + .blend (blend_v), + .in1 (texel_ul), + .in2 (texel_uh), + .out (texel_v) + ); + assign req_data[i] = req_filter ? texel_v : fmt_texels[0]; end assign stall_out = rsp_valid && ~rsp_ready; diff --git a/hw/rtl/tex_unit/VX_tex_unit.v b/hw/rtl/tex_unit/VX_tex_unit.v index 094c595e..921c49c2 100644 --- a/hw/rtl/tex_unit/VX_tex_unit.v +++ b/hw/rtl/tex_unit/VX_tex_unit.v @@ -190,7 +190,7 @@ module VX_tex_unit #( wire [`NR_BITS-1:0] rsp_rd; wire rsp_wb; - assign {rsp_format, rsp_u, rsp_v, rsp_rd, rsp_wb} = mem_rsp_info; + assign {rsp_u, rsp_v, rsp_format, rsp_rd, rsp_wb} = mem_rsp_info; VX_tex_sampler #( .CORE_ID (CORE_ID)