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instr_sched => ibuffer

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This commit is contained in:
Blaise Tine
2021-06-27 19:36:43 -07:00
parent 212581a33d
commit f84c8a0b5d
10 changed files with 117 additions and 114 deletions
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42
hw/rtl/VX_instr_sched.v → hw/rtl/VX_ibuffer.v
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@@ -1,6 +1,6 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_instr_sched #( module VX_ibuffer #(
parameter CORE_ID = 0 parameter CORE_ID = 0
) ( ) (
input wire clk, input wire clk,
@@ -10,7 +10,7 @@ module VX_instr_sched #(
VX_decode_if decode_if, VX_decode_if decode_if,
// outputs // outputs
VX_instr_sched_if instr_sched_if VX_ibuffer_if ibuffer_if
); );
`UNUSED_PARAM (CORE_ID) `UNUSED_PARAM (CORE_ID)
@@ -29,12 +29,12 @@ module VX_instr_sched #(
reg [`NUM_WARPS-1:0][DATAW-1:0] q_data_out; reg [`NUM_WARPS-1:0][DATAW-1:0] q_data_out;
wire enq_fire = decode_if.valid && decode_if.ready; wire enq_fire = decode_if.valid && decode_if.ready;
wire deq_fire = instr_sched_if.valid && instr_sched_if.ready; wire deq_fire = ibuffer_if.valid && ibuffer_if.ready;
for (genvar i = 0; i < `NUM_WARPS; ++i) begin for (genvar i = 0; i < `NUM_WARPS; ++i) begin
wire writing = enq_fire && (i == decode_if.wid); wire writing = enq_fire && (i == decode_if.wid);
wire reading = deq_fire && (i == instr_sched_if.wid); wire reading = deq_fire && (i == ibuffer_if.wid);
wire is_head_ptr = empty_r[i] || (alm_empty_r[i] && reading); wire is_head_ptr = empty_r[i] || (alm_empty_r[i] && reading);
@@ -182,22 +182,22 @@ module VX_instr_sched #(
decode_if.use_imm, decode_if.use_imm,
decode_if.used_regs}; decode_if.used_regs};
assign instr_sched_if.valid = deq_valid; assign ibuffer_if.valid = deq_valid;
assign instr_sched_if.wid = deq_wid; assign ibuffer_if.wid = deq_wid;
assign instr_sched_if.wid_n = deq_wid_n; assign ibuffer_if.wid_n = deq_wid_n;
assign {instr_sched_if.tmask, assign {ibuffer_if.tmask,
instr_sched_if.PC, ibuffer_if.PC,
instr_sched_if.ex_type, ibuffer_if.ex_type,
instr_sched_if.op_type, ibuffer_if.op_type,
instr_sched_if.op_mod, ibuffer_if.op_mod,
instr_sched_if.wb, ibuffer_if.wb,
instr_sched_if.rd, ibuffer_if.rd,
instr_sched_if.rs1, ibuffer_if.rs1,
instr_sched_if.rs2, ibuffer_if.rs2,
instr_sched_if.rs3, ibuffer_if.rs3,
instr_sched_if.imm, ibuffer_if.imm,
instr_sched_if.use_PC, ibuffer_if.use_PC,
instr_sched_if.use_imm, ibuffer_if.use_imm,
instr_sched_if.used_regs} = deq_instr; ibuffer_if.used_regs} = deq_instr;
endmodule endmodule

30
hw/rtl/VX_instr_demux.v
View File

@@ -5,7 +5,7 @@ module VX_instr_demux (
input wire reset, input wire reset,
// inputs // inputs
VX_instr_sched_if execute_if, VX_ibuffer_if ibuffer_if,
VX_gpr_rsp_if gpr_rsp_if, VX_gpr_rsp_if gpr_rsp_if,
// outputs // outputs
@@ -25,17 +25,17 @@ module VX_instr_demux (
VX_priority_encoder #( VX_priority_encoder #(
.N (`NUM_THREADS) .N (`NUM_THREADS)
) tid_select ( ) tid_select (
.data_in (execute_if.tmask), .data_in (ibuffer_if.tmask),
.index (tid), .index (tid),
`UNUSED_PIN (onehot), `UNUSED_PIN (onehot),
`UNUSED_PIN (valid_out) `UNUSED_PIN (valid_out)
); );
wire [31:0] next_PC = execute_if.PC + 4; wire [31:0] next_PC = ibuffer_if.PC + 4;
// ALU unit // ALU unit
wire alu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_ALU); wire alu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_ALU);
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BITS + `MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)) .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BITS + `MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32))
@@ -44,7 +44,7 @@ module VX_instr_demux (
.reset (reset), .reset (reset),
.valid_in (alu_req_valid), .valid_in (alu_req_valid),
.ready_in (alu_req_ready), .ready_in (alu_req_ready),
.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `ALU_OP(execute_if.op_type), execute_if.op_mod, execute_if.imm, execute_if.use_PC, execute_if.use_imm, execute_if.rd, execute_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, `ALU_OP(ibuffer_if.op_type), ibuffer_if.op_mod, ibuffer_if.imm, ibuffer_if.use_PC, ibuffer_if.use_imm, ibuffer_if.rd, ibuffer_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
.data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.op_mod, alu_req_if.imm, alu_req_if.use_PC, alu_req_if.use_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}), .data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.op_mod, alu_req_if.imm, alu_req_if.use_PC, alu_req_if.use_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}),
.valid_out (alu_req_if.valid), .valid_out (alu_req_if.valid),
.ready_out (alu_req_if.ready) .ready_out (alu_req_if.ready)
@@ -52,7 +52,7 @@ module VX_instr_demux (
// lsu unit // lsu unit
wire lsu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_LSU); wire lsu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_LSU);
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)) .DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32))
@@ -61,7 +61,7 @@ module VX_instr_demux (
.reset (reset), .reset (reset),
.valid_in (lsu_req_valid), .valid_in (lsu_req_valid),
.ready_in (lsu_req_ready), .ready_in (lsu_req_ready),
.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `LSU_OP(execute_if.op_type), execute_if.imm, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `LSU_OP(ibuffer_if.op_type), ibuffer_if.imm, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
.data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}), .data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}),
.valid_out (lsu_req_if.valid), .valid_out (lsu_req_if.valid),
.ready_out (lsu_req_if.ready) .ready_out (lsu_req_if.ready)
@@ -69,7 +69,7 @@ module VX_instr_demux (
// csr unit // csr unit
wire csr_req_valid = execute_if.valid && (execute_if.ex_type == `EX_CSR); wire csr_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_CSR);
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32) .DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32)
@@ -78,7 +78,7 @@ module VX_instr_demux (
.reset (reset), .reset (reset),
.valid_in (csr_req_valid), .valid_in (csr_req_valid),
.ready_in (csr_req_ready), .ready_in (csr_req_ready),
.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `CSR_OP(execute_if.op_type), execute_if.imm[`CSR_ADDR_BITS-1:0], execute_if.rd, execute_if.wb, execute_if.use_imm, execute_if.rs1, gpr_rsp_if.rs1_data[0]}), .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `CSR_OP(ibuffer_if.op_type), ibuffer_if.imm[`CSR_ADDR_BITS-1:0], ibuffer_if.rd, ibuffer_if.wb, ibuffer_if.use_imm, ibuffer_if.rs1, gpr_rsp_if.rs1_data[0]}),
.data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.use_imm, csr_req_if.rs1, csr_req_if.rs1_data}), .data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.use_imm, csr_req_if.rs1, csr_req_if.rs1_data}),
.valid_out (csr_req_if.valid), .valid_out (csr_req_if.valid),
.ready_out (csr_req_if.ready) .ready_out (csr_req_if.ready)
@@ -87,7 +87,7 @@ module VX_instr_demux (
// fpu unit // fpu unit
`ifdef EXT_F_ENABLE `ifdef EXT_F_ENABLE
wire fpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_FPU); wire fpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_FPU);
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)) .DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32))
@@ -96,7 +96,7 @@ module VX_instr_demux (
.reset (reset), .reset (reset),
.valid_in (fpu_req_valid), .valid_in (fpu_req_valid),
.ready_in (fpu_req_ready), .ready_in (fpu_req_ready),
.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `FPU_OP(execute_if.op_type), execute_if.op_mod, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}), .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `FPU_OP(ibuffer_if.op_type), ibuffer_if.op_mod, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}),
.data_out ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}), .data_out ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}),
.valid_out (fpu_req_if.valid), .valid_out (fpu_req_if.valid),
.ready_out (fpu_req_if.ready) .ready_out (fpu_req_if.ready)
@@ -108,7 +108,7 @@ module VX_instr_demux (
// gpu unit // gpu unit
wire gpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_GPU); wire gpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_GPU);
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32)) .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32))
@@ -117,7 +117,7 @@ module VX_instr_demux (
.reset (reset), .reset (reset),
.valid_in (gpu_req_valid), .valid_in (gpu_req_valid),
.ready_in (gpu_req_ready), .ready_in (gpu_req_ready),
.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `GPU_OP(execute_if.op_type), execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data[0]}), .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, next_PC, `GPU_OP(ibuffer_if.op_type), ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data[0]}),
.data_out ({gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.rs1_data, gpu_req_if.rs2_data}), .data_out ({gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.rs1_data, gpu_req_if.rs2_data}),
.valid_out (gpu_req_if.valid), .valid_out (gpu_req_if.valid),
.ready_out (gpu_req_if.ready) .ready_out (gpu_req_if.ready)
@@ -126,7 +126,7 @@ module VX_instr_demux (
// can take next request? // can take next request?
reg ready_r; reg ready_r;
always @(*) begin always @(*) begin
case (execute_if.ex_type) case (ibuffer_if.ex_type)
`EX_ALU: ready_r = alu_req_ready; `EX_ALU: ready_r = alu_req_ready;
`EX_LSU: ready_r = lsu_req_ready; `EX_LSU: ready_r = lsu_req_ready;
`EX_CSR: ready_r = csr_req_ready; `EX_CSR: ready_r = csr_req_ready;
@@ -135,6 +135,6 @@ module VX_instr_demux (
default: ready_r = 1'b1; // ignore NOPs default: ready_r = 1'b1; // ignore NOPs
endcase endcase
end end
assign execute_if.ready = ready_r; assign ibuffer_if.ready = ready_r;
endmodule endmodule

96
hw/rtl/VX_issue.v
View File

@@ -21,36 +21,36 @@ module VX_issue #(
VX_fpu_req_if fpu_req_if, VX_fpu_req_if fpu_req_if,
VX_gpu_req_if gpu_req_if VX_gpu_req_if gpu_req_if
); );
VX_instr_sched_if instr_sched_if(); VX_ibuffer_if ibuffer_if();
VX_instr_sched_if execute_if(); VX_ibuffer_if execute_if();
VX_gpr_req_if gpr_req_if(); VX_gpr_req_if gpr_req_if();
VX_gpr_rsp_if gpr_rsp_if(); VX_gpr_rsp_if gpr_rsp_if();
wire scoreboard_delay; wire scoreboard_delay;
VX_instr_sched #( VX_ibuffer #(
.CORE_ID(CORE_ID) .CORE_ID(CORE_ID)
) instr_sched ( ) ibuffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.decode_if (decode_if), .decode_if (decode_if),
.instr_sched_if (instr_sched_if) .ibuffer_if (ibuffer_if)
); );
VX_scoreboard #( VX_scoreboard #(
.CORE_ID(CORE_ID) .CORE_ID(CORE_ID)
) scoreboard ( ) scoreboard (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.instr_sched_if (instr_sched_if), .ibuffer_if (ibuffer_if),
.writeback_if (writeback_if), .writeback_if(writeback_if),
.delay (scoreboard_delay) .delay (scoreboard_delay)
); );
assign gpr_req_if.wid = instr_sched_if.wid; assign gpr_req_if.wid = ibuffer_if.wid;
assign gpr_req_if.rs1 = instr_sched_if.rs1; assign gpr_req_if.rs1 = ibuffer_if.rs1;
assign gpr_req_if.rs2 = instr_sched_if.rs2; assign gpr_req_if.rs2 = ibuffer_if.rs2;
assign gpr_req_if.rs3 = instr_sched_if.rs3; assign gpr_req_if.rs3 = ibuffer_if.rs3;
VX_gpr_stage #( VX_gpr_stage #(
.CORE_ID(CORE_ID) .CORE_ID(CORE_ID)
@@ -62,24 +62,24 @@ module VX_issue #(
.gpr_rsp_if (gpr_rsp_if) .gpr_rsp_if (gpr_rsp_if)
); );
assign execute_if.valid = instr_sched_if.valid && ~scoreboard_delay; assign execute_if.valid = ibuffer_if.valid && ~scoreboard_delay;
assign execute_if.wid = instr_sched_if.wid; assign execute_if.wid = ibuffer_if.wid;
assign execute_if.tmask = instr_sched_if.tmask; assign execute_if.tmask = ibuffer_if.tmask;
assign execute_if.PC = instr_sched_if.PC; assign execute_if.PC = ibuffer_if.PC;
assign execute_if.ex_type = instr_sched_if.ex_type; assign execute_if.ex_type = ibuffer_if.ex_type;
assign execute_if.op_type = instr_sched_if.op_type; assign execute_if.op_type = ibuffer_if.op_type;
assign execute_if.op_mod = instr_sched_if.op_mod; assign execute_if.op_mod = ibuffer_if.op_mod;
assign execute_if.wb = instr_sched_if.wb; assign execute_if.wb = ibuffer_if.wb;
assign execute_if.rd = instr_sched_if.rd; assign execute_if.rd = ibuffer_if.rd;
assign execute_if.rs1 = instr_sched_if.rs1; assign execute_if.rs1 = ibuffer_if.rs1;
assign execute_if.imm = instr_sched_if.imm; assign execute_if.imm = ibuffer_if.imm;
assign execute_if.use_PC = instr_sched_if.use_PC; assign execute_if.use_PC = ibuffer_if.use_PC;
assign execute_if.use_imm = instr_sched_if.use_imm; assign execute_if.use_imm = ibuffer_if.use_imm;
VX_instr_demux instr_demux ( VX_instr_demux instr_demux (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.execute_if (execute_if), .ibuffer_if (execute_if),
.gpr_rsp_if (gpr_rsp_if), .gpr_rsp_if (gpr_rsp_if),
.alu_req_if (alu_req_if), .alu_req_if (alu_req_if),
.lsu_req_if (lsu_req_if), .lsu_req_if (lsu_req_if),
@@ -89,23 +89,23 @@ module VX_issue #(
); );
// issue the instruction // issue the instruction
assign instr_sched_if.ready = !scoreboard_delay && execute_if.ready; assign ibuffer_if.ready = !scoreboard_delay && execute_if.ready;
`SCOPE_ASSIGN (issue_fire, instr_sched_if.valid && instr_sched_if.ready); `SCOPE_ASSIGN (issue_fire, ibuffer_if.valid && ibuffer_if.ready);
`SCOPE_ASSIGN (issue_wid, instr_sched_if.wid); `SCOPE_ASSIGN (issue_wid, ibuffer_if.wid);
`SCOPE_ASSIGN (issue_tmask, instr_sched_if.tmask); `SCOPE_ASSIGN (issue_tmask, ibuffer_if.tmask);
`SCOPE_ASSIGN (issue_pc, instr_sched_if.PC); `SCOPE_ASSIGN (issue_pc, ibuffer_if.PC);
`SCOPE_ASSIGN (issue_ex_type, instr_sched_if.ex_type); `SCOPE_ASSIGN (issue_ex_type, ibuffer_if.ex_type);
`SCOPE_ASSIGN (issue_op_type, instr_sched_if.op_type); `SCOPE_ASSIGN (issue_op_type, ibuffer_if.op_type);
`SCOPE_ASSIGN (issue_op_mod, instr_sched_if.op_mod); `SCOPE_ASSIGN (issue_op_mod, ibuffer_if.op_mod);
`SCOPE_ASSIGN (issue_wb, instr_sched_if.wb); `SCOPE_ASSIGN (issue_wb, ibuffer_if.wb);
`SCOPE_ASSIGN (issue_rd, instr_sched_if.rd); `SCOPE_ASSIGN (issue_rd, ibuffer_if.rd);
`SCOPE_ASSIGN (issue_rs1, instr_sched_if.rs1); `SCOPE_ASSIGN (issue_rs1, ibuffer_if.rs1);
`SCOPE_ASSIGN (issue_rs2, instr_sched_if.rs2); `SCOPE_ASSIGN (issue_rs2, ibuffer_if.rs2);
`SCOPE_ASSIGN (issue_rs3, instr_sched_if.rs3); `SCOPE_ASSIGN (issue_rs3, ibuffer_if.rs3);
`SCOPE_ASSIGN (issue_imm, instr_sched_if.imm); `SCOPE_ASSIGN (issue_imm, ibuffer_if.imm);
`SCOPE_ASSIGN (issue_use_pc, instr_sched_if.use_PC); `SCOPE_ASSIGN (issue_use_pc, ibuffer_if.use_PC);
`SCOPE_ASSIGN (issue_use_imm, instr_sched_if.use_imm); `SCOPE_ASSIGN (issue_use_imm, ibuffer_if.use_imm);
`SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay); `SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay);
`SCOPE_ASSIGN (execute_delay, ~execute_if.ready); `SCOPE_ASSIGN (execute_delay, ~execute_if.ready);
`SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data); `SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data);
@@ -145,7 +145,7 @@ module VX_issue #(
if (decode_if.valid & !decode_if.ready) begin if (decode_if.valid & !decode_if.ready) begin
perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'd1; perf_ibf_stalls <= perf_ibf_stalls + `PERF_CTR_BITS'd1;
end end
if (instr_sched_if.valid & scoreboard_delay) begin if (ibuffer_if.valid & scoreboard_delay) begin
perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'd1; perf_scb_stalls <= perf_scb_stalls + `PERF_CTR_BITS'd1;
end end
if (alu_req_if.valid & !alu_req_if.ready) begin if (alu_req_if.valid & !alu_req_if.ready) begin

24
hw/rtl/VX_scoreboard.v
View File

@@ -6,7 +6,7 @@ module VX_scoreboard #(
input wire clk, input wire clk,
input wire reset, input wire reset,
VX_instr_sched_if instr_sched_if, VX_ibuffer_if ibuffer_if,
VX_writeback_if writeback_if, VX_writeback_if writeback_if,
output wire delay output wire delay
); );
@@ -14,16 +14,16 @@ module VX_scoreboard #(
reg [`NUM_REGS-1:0] deq_inuse_regs; reg [`NUM_REGS-1:0] deq_inuse_regs;
assign delay = |(deq_inuse_regs & instr_sched_if.used_regs); assign delay = |(deq_inuse_regs & ibuffer_if.used_regs);
wire reserve_reg = instr_sched_if.valid && instr_sched_if.ready && instr_sched_if.wb; wire reserve_reg = ibuffer_if.valid && ibuffer_if.ready && ibuffer_if.wb;
wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop; wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop;
always @(*) begin always @(*) begin
inuse_regs_n = inuse_regs; inuse_regs_n = inuse_regs;
if (reserve_reg) begin if (reserve_reg) begin
inuse_regs_n[instr_sched_if.wid][instr_sched_if.rd] = 1; inuse_regs_n[ibuffer_if.wid][ibuffer_if.rd] = 1;
end end
if (release_reg) begin if (release_reg) begin
inuse_regs_n[writeback_if.wid][writeback_if.rd] = 0; inuse_regs_n[writeback_if.wid][writeback_if.rd] = 0;
@@ -36,7 +36,7 @@ module VX_scoreboard #(
end else begin end else begin
inuse_regs <= inuse_regs_n; inuse_regs <= inuse_regs_n;
end end
deq_inuse_regs <= inuse_regs_n[instr_sched_if.wid_n]; deq_inuse_regs <= inuse_regs_n[ibuffer_if.wid_n];
end end
reg [31:0] deadlock_ctr; reg [31:0] deadlock_ctr;
@@ -46,10 +46,10 @@ module VX_scoreboard #(
deadlock_ctr <= 0; deadlock_ctr <= 0;
end else begin end else begin
`ifdef DBG_PRINT_PIPELINE `ifdef DBG_PRINT_PIPELINE
if (instr_sched_if.valid && ~instr_sched_if.ready) begin if (ibuffer_if.valid && ~ibuffer_if.ready) begin
$display("%t: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b", $display("%t: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
$time, CORE_ID, instr_sched_if.wid, instr_sched_if.PC, instr_sched_if.rd, instr_sched_if.wb, $time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb,
deq_inuse_regs[instr_sched_if.rd], deq_inuse_regs[instr_sched_if.rs1], deq_inuse_regs[instr_sched_if.rs2], deq_inuse_regs[instr_sched_if.rs3]); deq_inuse_regs[ibuffer_if.rd], deq_inuse_regs[ibuffer_if.rs1], deq_inuse_regs[ibuffer_if.rs2], deq_inuse_regs[ibuffer_if.rs3]);
end end
`endif `endif
if (release_reg) begin if (release_reg) begin
@@ -57,12 +57,12 @@ module VX_scoreboard #(
else $error("%t: *** core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d", else $error("%t: *** core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d",
$time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd); $time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd);
end end
if (instr_sched_if.valid && ~instr_sched_if.ready) begin if (ibuffer_if.valid && ~ibuffer_if.ready) begin
deadlock_ctr <= deadlock_ctr + 1; deadlock_ctr <= deadlock_ctr + 1;
assert(deadlock_ctr < deadlock_timeout) else $error("%t: *** core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b", assert(deadlock_ctr < deadlock_timeout) else $error("%t: *** core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
$time, CORE_ID, instr_sched_if.wid, instr_sched_if.PC, instr_sched_if.rd, instr_sched_if.wb, $time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb,
deq_inuse_regs[instr_sched_if.rd], deq_inuse_regs[instr_sched_if.rs1], deq_inuse_regs[instr_sched_if.rs2], deq_inuse_regs[instr_sched_if.rs3]); deq_inuse_regs[ibuffer_if.rd], deq_inuse_regs[ibuffer_if.rs1], deq_inuse_regs[ibuffer_if.rs2], deq_inuse_regs[ibuffer_if.rs3]);
end else if (instr_sched_if.valid && instr_sched_if.ready) begin end else if (ibuffer_if.valid && ibuffer_if.ready) begin
deadlock_ctr <= 0; deadlock_ctr <= 0;
end end
end end

3
hw/rtl/afu/vortex_afu.sv
View File

@@ -534,7 +534,8 @@ VX_mem_arb #(
.DATA_WIDTH (LMEM_LINE_WIDTH), .DATA_WIDTH (LMEM_LINE_WIDTH),
.ADDR_WIDTH (LMEM_ADDR_WIDTH), .ADDR_WIDTH (LMEM_ADDR_WIDTH),
.TAG_IN_WIDTH (AVS_REQ_TAGW), .TAG_IN_WIDTH (AVS_REQ_TAGW),
.TYPE ("X") .BUFFERED_REQ (1),
.BUFFERED_RSP (1)
) mem_arb ( ) mem_arb (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

6
hw/rtl/cache/VX_bank.v vendored
View File

@@ -437,10 +437,12 @@ module VX_bank #(
`UNUSED_PIN (enqueue_almfull), `UNUSED_PIN (enqueue_almfull),
`UNUSED_PIN (enqueue_full), `UNUSED_PIN (enqueue_full),
// lookup // lookup
.lookup_ready (mrsq_pop),
.lookup_addr (lookup_addr), .lookup_addr (lookup_addr),
.lookup_match (mshr_pending), .lookup_match (mshr_pending),
// fill update
.fill_update (mrsq_pop),
// schedule // schedule
.schedule (mshr_pop), .schedule (mshr_pop),

16
hw/rtl/cache/VX_miss_resrv.v vendored
View File

@@ -42,11 +42,13 @@ module VX_miss_resrv #(
output wire enqueue_full, output wire enqueue_full,
output wire enqueue_almfull, output wire enqueue_almfull,
// lookup // lookup
input wire lookup_ready,
input wire [`LINE_ADDR_WIDTH-1:0] lookup_addr, input wire [`LINE_ADDR_WIDTH-1:0] lookup_addr,
output wire lookup_match, output wire lookup_match,
// fill update
input wire fill_update,
// schedule // schedule
input wire schedule, input wire schedule,
output wire schedule_valid, output wire schedule_valid,
@@ -74,8 +76,6 @@ module VX_miss_resrv #(
assign valid_address_match[i] = valid_table[i] && (addr_table[i] == lookup_addr); assign valid_address_match[i] = valid_table[i] && (addr_table[i] == lookup_addr);
end end
assign lookup_match = (| valid_address_match);
wire push_new = enqueue && !enqueue_is_mshr; wire push_new = enqueue && !enqueue_is_mshr;
wire restore = enqueue && enqueue_is_mshr; wire restore = enqueue && enqueue_is_mshr;
@@ -93,10 +93,9 @@ module VX_miss_resrv #(
used_r <= 0; used_r <= 0;
alm_full_r <= 0; alm_full_r <= 0;
full_r <= 0; full_r <= 0;
end else begin end else begin
// WARNING: lookup should happen enqueue for ready_table's correct update if (fill_update) begin
if (lookup_ready) begin
// unlock pending requests for scheduling // unlock pending requests for scheduling
ready_table <= ready_table | valid_address_match; ready_table <= ready_table | valid_address_match;
end end
@@ -170,6 +169,7 @@ module VX_miss_resrv #(
.dout(schedule_data) .dout(schedule_data)
); );
assign lookup_match = (| valid_address_match);
assign schedule_valid = ready_table[schedule_ptr]; assign schedule_valid = ready_table[schedule_ptr];
assign schedule_addr = addr_table[schedule_ptr]; assign schedule_addr = addr_table[schedule_ptr];
assign enqueue_almfull = alm_full_r; assign enqueue_almfull = alm_full_r;
@@ -177,7 +177,7 @@ module VX_miss_resrv #(
`ifdef DBG_PRINT_CACHE_MSHR `ifdef DBG_PRINT_CACHE_MSHR
always @(posedge clk) begin always @(posedge clk) begin
if (lookup_ready || schedule || enqueue || dequeue) begin if (fill_update || schedule || enqueue || dequeue) begin
if (schedule) if (schedule)
$display("%t: cache%0d:%0d mshr-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(schedule_addr, BANK_ID), deq_debug_wid, deq_debug_pc); $display("%t: cache%0d:%0d mshr-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(schedule_addr, BANK_ID), deq_debug_wid, deq_debug_pc);
if (enqueue) begin if (enqueue) begin

6
hw/rtl/interfaces/VX_instr_sched_if.v → hw/rtl/interfaces/VX_ibuffer_if.v
View File

@@ -1,9 +1,9 @@
`ifndef VX_INSTR_SCHED_IF `ifndef VX_IBUFFER_IF
`define VX_INSTR_SCHED_IF `define VX_IBUFFER_IF
`include "VX_define.vh" `include "VX_define.vh"
interface VX_instr_sched_if (); interface VX_ibuffer_if ();
wire valid; wire valid;
wire [`NW_BITS-1:0] wid; wire [`NW_BITS-1:0] wid;

4
hw/syn/opae/vortex_afu.json
View File

@@ -2,8 +2,8 @@
"version": 1, "version": 1,
"afu-image": { "afu-image": {
"power": 0, "power": 0,
"clock-frequency-high": "auto-210", "clock-frequency-high": "auto",
"clock-frequency-low": "auto-210", "clock-frequency-low": "auto",
"cmd-mem-read": 1, "cmd-mem-read": 1,
"cmd-mem-write": 2, "cmd-mem-write": 2,

4
hw/syn/quartus/Makefile
View File

@@ -5,7 +5,7 @@ BUILDIR ?= build
unittest: unittest:
mkdir -p unittest/$(BUILDIR) mkdir -p unittest/$(BUILDIR)
cp unittest/Makefile unittest/$(BUILDIR) cp unittest/Makefile unittest/$(BUILDIR)
$(MAKE) -C unittest/$(BUILDIR) clean && $(MAKE) -C unittest/$(BUILDIR) > unittest//$(BUILDIR)build.log 2>&1 & $(MAKE) -C unittest/$(BUILDIR) clean && $(MAKE) -C unittest/$(BUILDIR) > unittest/$(BUILDIR)/build.log 2>&1 &
pipeline: pipeline:
mkdir -p pipeline/$(BUILDIR) mkdir -p pipeline/$(BUILDIR)
@@ -55,7 +55,7 @@ top8:
top16: top16:
mkdir -p top16/$(BUILDIR) mkdir -p top16/$(BUILDIR)
cp top16/Makefile top16/$(BUILDIR) cp top16/Makefile top16/$(BUILDIR)
$(MAKE) -C top16/$(BUILDIR) clean && $(MAKE) -C top16/$(BUILDIR) > top16/$(BUILDIR)build.log 2>&1 & $(MAKE) -C top16/$(BUILDIR) clean && $(MAKE) -C top16/$(BUILDIR) > top16/$(BUILDIR)/build.log 2>&1 &
top32: top32:
mkdir -p top32/$(BUILDIR) mkdir -p top32/$(BUILDIR)