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instr_sched => ibuffer

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Blaise Tine
2021-06-27 19:36:43 -07:00
parent 212581a33d
commit f84c8a0b5d
10 changed files with 117 additions and 114 deletions
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24
hw/rtl/VX_scoreboard.v
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@@ -6,7 +6,7 @@ module VX_scoreboard #(
input wire clk,
input wire reset,
VX_instr_sched_if instr_sched_if,
VX_ibuffer_if ibuffer_if,
VX_writeback_if writeback_if,
output wire delay
);
@@ -14,16 +14,16 @@ module VX_scoreboard #(
reg [`NUM_REGS-1:0] deq_inuse_regs;
assign delay = |(deq_inuse_regs & instr_sched_if.used_regs);
assign delay = |(deq_inuse_regs & ibuffer_if.used_regs);
wire reserve_reg = instr_sched_if.valid && instr_sched_if.ready && instr_sched_if.wb;
wire reserve_reg = ibuffer_if.valid && ibuffer_if.ready && ibuffer_if.wb;
wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop;
always @(*) begin
inuse_regs_n = inuse_regs;
if (reserve_reg) begin
inuse_regs_n[instr_sched_if.wid][instr_sched_if.rd] = 1;
inuse_regs_n[ibuffer_if.wid][ibuffer_if.rd] = 1;
end
if (release_reg) begin
inuse_regs_n[writeback_if.wid][writeback_if.rd] = 0;
@@ -36,7 +36,7 @@ module VX_scoreboard #(
end else begin
inuse_regs <= inuse_regs_n;
end
deq_inuse_regs <= inuse_regs_n[instr_sched_if.wid_n];
deq_inuse_regs <= inuse_regs_n[ibuffer_if.wid_n];
end
reg [31:0] deadlock_ctr;
@@ -46,10 +46,10 @@ module VX_scoreboard #(
deadlock_ctr <= 0;
end else begin
`ifdef DBG_PRINT_PIPELINE
if (instr_sched_if.valid && ~instr_sched_if.ready) begin
if (ibuffer_if.valid && ~ibuffer_if.ready) begin
$display("%t: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
$time, CORE_ID, instr_sched_if.wid, instr_sched_if.PC, instr_sched_if.rd, instr_sched_if.wb,
deq_inuse_regs[instr_sched_if.rd], deq_inuse_regs[instr_sched_if.rs1], deq_inuse_regs[instr_sched_if.rs2], deq_inuse_regs[instr_sched_if.rs3]);
$time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb,
deq_inuse_regs[ibuffer_if.rd], deq_inuse_regs[ibuffer_if.rs1], deq_inuse_regs[ibuffer_if.rs2], deq_inuse_regs[ibuffer_if.rs3]);
end
`endif
if (release_reg) begin
@@ -57,12 +57,12 @@ module VX_scoreboard #(
else $error("%t: *** core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d",
$time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd);
end
if (instr_sched_if.valid && ~instr_sched_if.ready) begin
if (ibuffer_if.valid && ~ibuffer_if.ready) begin
deadlock_ctr <= deadlock_ctr + 1;
assert(deadlock_ctr < deadlock_timeout) else $error("%t: *** core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
$time, CORE_ID, instr_sched_if.wid, instr_sched_if.PC, instr_sched_if.rd, instr_sched_if.wb,
deq_inuse_regs[instr_sched_if.rd], deq_inuse_regs[instr_sched_if.rs1], deq_inuse_regs[instr_sched_if.rs2], deq_inuse_regs[instr_sched_if.rs3]);
end else if (instr_sched_if.valid && instr_sched_if.ready) begin
$time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb,
deq_inuse_regs[ibuffer_if.rd], deq_inuse_regs[ibuffer_if.rs1], deq_inuse_regs[ibuffer_if.rs2], deq_inuse_regs[ibuffer_if.rs3]);
end else if (ibuffer_if.valid && ibuffer_if.ready) begin
deadlock_ctr <= 0;
end
end