simX within 30% cycles of the RTL for matAdd

simX/include/core.h

@@ -19,9 +19,9 @@
 #include "Vcache_simX.h"
 #include "verilated.h"
 
-#ifdef VCD_OUTPUT
+// #ifdef VCD_OUTPUT
 #include <verilated_vcd_c.h>
-#endif
+// #endif
 
 
 #include "trace.h"
@@ -92,17 +92,34 @@ namespace Harp {
   public:
     Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id=0);
 
-    Vcache_simX * cache_simulator;
+    Vcache_simX   * cache_simulator;
+    VerilatedVcdC * m_trace;
+
+    bool renameTable[32][32];
+    bool stallWarp[32];
+    bool foundSchedule;
+
+    trace_inst_t inst_in_fetch;
+    trace_inst_t inst_in_decode;
+    trace_inst_t inst_in_scheduler;
+    trace_inst_t inst_in_exe;
+    trace_inst_t inst_in_lsu;
+    trace_inst_t inst_in_wb;
+
+    bool release_warp;
+    int release_warp_num;
 
     bool interrupt(Word r0);
     bool running() const;
 
+    void getCacheDelays(trace_inst_t *);
+    void warpScheduler();
     void fetch();
     void decode();
     void scheduler();
-    void gpr_read();
     void execute_unit();
     void load_store();
+    void writeback();
 
     void step();
 
@@ -117,6 +134,7 @@ namespace Harp {
     unsigned long steps;
     std::vector<Warp> w;
     std::map<Word, std::set<Warp *> > b; // Barriers
+    int schedule_w;
   };
 
   class Warp {

simX/include/instruction.h

@@ -8,7 +8,7 @@
 #include <iostream>
 
 #include "types.h"
-
+#include "trace.h"
 namespace Harp {
   class Warp;
   class Ref;
@@ -79,7 +79,7 @@ namespace Harp {
       {
       }
 
-    void executeOn(Warp &warp);
+    void executeOn(Warp &warp, trace_inst_t *);
     friend std::ostream &operator<<(std::ostream &, Instruction &);
 
     /* Setters used to "craft" the instruction. */

simX/include/trace.h

@@ -28,6 +28,9 @@ namespace Harp {
 
     // Instruction execute
     bool stall_warp;
+    bool wspawn;
+
+    bool stalled;
   } trace_inst_t;
 
 }