From f575f16f57df3a7fb253d283e332f7e2609a5935 Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@iam-ssh1.research.intel-research.net>
Date: Tue, 1 Dec 2020 12:57:02 -0800
Subject: [PATCH] minor update

---
 hw/rtl/VX_csr_arb.v          | 2 +-
 hw/rtl/VX_opd_collect.v      | 2 ++
 hw/rtl/libs/VX_skid_buffer.v | 2 ++
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/rtl/VX_csr_arb.v b/hw/rtl/VX_csr_arb.v
index 9ba8a364..1dfd7dfc 100644
--- a/hw/rtl/VX_csr_arb.v
+++ b/hw/rtl/VX_csr_arb.v
@@ -55,7 +55,7 @@ module VX_csr_arb (
     assign csr_rsp_if.ready = select_io_rsp ? csr_io_rsp_tmp_if.ready : csr_commit_if.ready;
 
     // Use skid buffer on CSR IO bus to stop backpressure delay propagation
-    VX_elastic_buffer #(
+    VX_skid_buffer #(
         .DATAW (32)
     ) io_skid_buffer (
         .clk       (clk),
diff --git a/hw/rtl/VX_opd_collect.v b/hw/rtl/VX_opd_collect.v
index 8b4210ae..1c71ef84 100644
--- a/hw/rtl/VX_opd_collect.v
+++ b/hw/rtl/VX_opd_collect.v
@@ -7,10 +7,12 @@ module VX_opd_collect #(
 ) ( 
     input  wire             clk,
     input  wire             reset,
+    
     input  wire             valid_in,
     output wire             ready_in,        
     input  wire [INSTW-1:0] inst_in,
     input  wire [OPDSW-1:0] opds_in,
+
     output wire [INSTW+OPDSW-1:0] data_out,
     output wire             valid_out,    
     input  wire             ready_out
diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v
index 53319175..a7a412fb 100644
--- a/hw/rtl/libs/VX_skid_buffer.v
+++ b/hw/rtl/libs/VX_skid_buffer.v
@@ -5,9 +5,11 @@ module VX_skid_buffer #(
 ) ( 
     input  wire             clk,
     input  wire             reset,
+    
     input  wire             valid_in,
     output wire             ready_in,        
     input  wire [DATAW-1:0] data_in,
+
     output wire [DATAW-1:0] data_out,
     input  wire             ready_out,
     output wire             valid_out