quartus projects

hw/modelsim/vortex_tb.v

@@ -82,8 +82,6 @@ reg[31:0]  io_data;
 
 	reg[31:0] hi;
 
-	integer temp;
-
 	initial begin
 		// $fdumpfile("vortex1.vcd");
 		load_file("../../runtime/tests/simple/simple_main_if.hex");
@@ -104,18 +102,18 @@ reg[31:0]  io_data;
 		.io_data                      (io_data),
 		.m_read_addr_d                (o_m_read_addr_d),
 		.m_evict_addr_d               (o_m_evict_addr_d),
-		.m_valid_d                  (o_m_valid_d),
+		.m_valid_d                    (o_m_valid_d),
-		.m_writedata_d              (o_m_writedata_d),
+		.m_writedata_d                (o_m_writedata_d),
-		.m_read_or_write_d          (o_m_read_or_write_d),
+		.m_read_or_write_d            (o_m_read_or_write_d),
-		.m_readdata_d               (i_m_readdata_d),
+		.m_readdata_d                 (i_m_readdata_d),
-		.m_ready_d                  (i_m_ready_d),
+		.m_ready_d                    (i_m_ready_d),
-		.m_read_addr                (o_m_read_addr_i),
+		.m_read_addr                  (o_m_read_addr_i),
-		.m_evict_addr               (o_m_evict_addr_i),
+		.m_evict_addr                 (o_m_evict_addr_i),
-		.m_valid                    (o_m_valid_i),
+		.m_valid                      (o_m_valid_i),
-		.writedata                (o_m_writedata_i),
+		.writedata                    (o_m_writedata_i),
-		.m_read_or_write            (o_m_read_or_write_i),
+		.m_read_or_write              (o_m_read_or_write_i),
-		.m_readdata                 (i_m_readdata_i),
+		.m_readdata                   (i_m_readdata_i),
-		.m_ready                    (i_m_ready_i),
+		.m_ready                      (i_m_ready_i),
 		.ebreak                       (out_ebreak)
 	);
 

hw/rtl/VX_alu.v

@@ -123,7 +123,8 @@ module VX_alu_unit (
         end
     end
 
-    `ifdef SYN_FUNC
+ `ifdef SYN_FUNC
+ 
     wire which_in2;
     wire[31:0] upper_immed;
 
@@ -205,4 +206,4 @@ module VX_alu_unit (
 
 `endif
 
-endmodule : VX_alu
+endmodule

hw/rtl/VX_define.vh

@@ -140,6 +140,9 @@
 // IO BUS
 `define IO_BUS_ADDR 32'h00010000
 
+// Program startup address
+`define STARTUP_ADDR 32'h80000000
+
 ////////////////////////// Dcache Configurable Knobs //////////////////////////
 
 // Function ID

hw/rtl/VX_exec_unit.v

@@ -47,7 +47,7 @@ module VX_exec_unit (
     genvar index_out_reg;
     generate
         for (index_out_reg = 0; index_out_reg < `NUM_THREADS; index_out_reg = index_out_reg + 1) begin : alu_defs
-            VX_alu alu(
+            VX_alu_unit alu_unit (
                 .clk            (clk),
                 .reset          (reset),
                 .src_a          (in_a_reg_data[index_out_reg]),

hw/rtl/VX_fetch.v

@@ -18,9 +18,9 @@ module VX_fetch (
 );
 
     wire[`NUM_THREADS-1:0] thread_mask;
-    wire[`NW_BITS-1:0] warp_num;
+    wire[`NW_BITS-1:0]     warp_num;
-    wire[31:0]     warp_pc;
+    wire[31:0]             warp_pc;
-    wire           scheduled_warp;
+    wire                   scheduled_warp;
 
     wire pipe_stall;
 

hw/rtl/VX_icache_stage.v

@@ -44,11 +44,11 @@ module VX_icache_stage (
     // Core can't accept response
     assign icache_rsp_if.core_rsp_ready = ~total_freeze;
 
-    integer curr_w;
+    integer w;
     always @(posedge clk) begin
         if (reset) begin
-            for (curr_w = 0; curr_w < `NUM_WARPS; curr_w=curr_w+1) begin
+            for (w = 0; w < `NUM_WARPS; w=w+1) begin
-                threads_active[curr_w] <= 0;
+                threads_active[w] <= 0;
             end
         end else begin
             if (valid_inst && !icache_stage_delay) begin

hw/rtl/VX_scheduler.v

@@ -47,8 +47,8 @@ module VX_scheduler (
                          || (gpr_stage_delay && (is_mem || is_exec))
                          || (exec_delay && is_exec);
 
-    integer i;
+    integer i, w;
-    integer w;
+    
     always @(posedge clk) begin
 
         if (reset) begin

hw/rtl/VX_warp.v

@@ -25,12 +25,12 @@ module VX_warp (
     reg [`NUM_THREADS-1:0] valid_t;
     reg [`NUM_THREADS-1:0] valid_zero;
 
-    integer ini_cur_th = 0;
+    integer ti;
     initial begin
         real_PC = 0;
-        for (ini_cur_th = 1; ini_cur_th < `NUM_THREADS; ini_cur_th=ini_cur_th+1) begin
+        for (ti = 1; ti < `NUM_THREADS; ti=ti+1) begin
-            valid_t[ini_cur_th]    = 0; // Thread 1 active
+            valid_t[ti]    = 0; // Thread 1 active
-            valid_zero[ini_cur_th] = 0;
+            valid_zero[ti] = 0;
         end
         valid_t       = 1;
         valid_zero[0] = 0;
@@ -44,10 +44,10 @@ module VX_warp (
         end
     end
 
-    genvar out_cur_th;
+    genvar tv;
     generate
-        for (out_cur_th = 0; out_cur_th < `NUM_THREADS; out_cur_th = out_cur_th+1) begin : valid_assign
+        for (tv = 0; tv < `NUM_THREADS; tv = tv+1) begin : valid_assign
-            assign valid[out_cur_th] = change_mask ? thread_mask[out_cur_th] : stall ? 1'b0  : valid_t[out_cur_th];
+            assign valid[tv] = change_mask ? thread_mask[tv] : stall ? 1'b0  : valid_t[tv];
         end
     endgenerate
 

hw/rtl/VX_warp_sched.v

@@ -87,20 +87,20 @@ module VX_warp_sched (
 
     wire wstall_this_cycle;
 
-    reg[`NUM_THREADS-1:0] thread_masks[`NUM_WARPS-1:0];
+    reg [`NUM_THREADS-1:0] thread_masks[`NUM_WARPS-1:0];
-    reg[31:0]     warp_pcs[`NUM_WARPS-1:0];
+    reg [31:0] warp_pcs[`NUM_WARPS-1:0];
 
     // barriers
-    reg[`NUM_WARPS-1:0] barrier_stall_mask[(`NUM_BARRIERS-1):0];
+    reg [`NUM_WARPS-1:0] barrier_stall_mask[(`NUM_BARRIERS-1):0];
-    wire         reached_barrier_limit;
+    wire reached_barrier_limit;
-    wire[`NUM_WARPS-1:0] curr_barrier_mask;
+    wire [`NUM_WARPS-1:0] b_mask;
-    wire[$clog2(`NUM_WARPS):0] curr_barrier_count;
+    wire [$clog2(`NUM_WARPS):0] b_count;
 
     // wsapwn
-    reg[31:0]    use_wsapwn_pc;
+    reg [31:0]    use_wsapwn_pc;
-    reg[`NUM_WARPS-1:0] use_wsapwn;
+    reg [`NUM_WARPS-1:0] use_wsapwn;
 
-    wire[`NW_BITS-1:0] warp_to_schedule;
+    wire [`NW_BITS-1:0] warp_to_schedule;
     wire           schedule;
 
     wire hazard;
@@ -108,22 +108,22 @@ module VX_warp_sched (
 
     wire real_schedule;
 
-    wire[31:0] new_pc;
+    wire [31:0] new_pc;
 
-    reg[`NUM_WARPS-1:0] total_barrier_stall;
+    reg [`NUM_WARPS-1:0] total_barrier_stall;
 
     reg didnt_split;
 
-    integer curr_w_help;
+    integer w, b;
-    integer curr_barrier;
+    
     always @(posedge clk) begin
         if (reset) begin
-            for (curr_barrier = 0; curr_barrier < `NUM_BARRIERS; curr_barrier=curr_barrier+1) begin
+            for (b = 0; b < `NUM_BARRIERS; b=b+1) begin
-                barrier_stall_mask[curr_barrier] <= 0;
+                barrier_stall_mask[b] <= 0;
             end
             use_wsapwn_pc         <= 0;
             use_wsapwn            <= 0;
-            warp_pcs[0]           <= (32'h80000000 - 4);
+            warp_pcs[0]           <= (`STARTUP_ADDR - 4);
             warp_active[0]        <= 1; // Activating first warp
             visible_active[0]     <= 1; // Activating first warp
             thread_masks[0]       <= 1; // Activating first thread in first warp
@@ -131,11 +131,11 @@ module VX_warp_sched (
             didnt_split           <= 0;
             warp_lock             <= 0;      
             // total_barrier_stall    = 0;
-            for (curr_w_help = 1; curr_w_help < `NUM_WARPS; curr_w_help=curr_w_help+1) begin
+            for (w = 1; w < `NUM_WARPS; w=w+1) begin
-                warp_pcs[curr_w_help]        <= 0;
+                warp_pcs[w]        <= 0;
-                warp_active[curr_w_help]     <= 0; // Activating first warp
+                warp_active[w]     <= 0; // Activating first warp
-                visible_active[curr_w_help]  <= 0; // Activating first warp
+                visible_active[w]  <= 0; // Activating first warp
-                thread_masks[curr_w_help]    <= 1; // Activating first thread in first warp
+                thread_masks[w]    <= 1; // Activating first thread in first warp
             end
 
         end else begin
@@ -228,8 +228,8 @@ module VX_warp_sched (
     VX_countones #(
         .N(`NUM_WARPS)
     ) barrier_count (
-        .valids(curr_barrier_mask),
+        .valids(b_mask),
-        .count (curr_barrier_count)
+        .count (b_count)
     );
 
     wire [$clog2(`NUM_WARPS):0] count_visible_active;
@@ -241,10 +241,10 @@ module VX_warp_sched (
         .count (count_visible_active)
     );
 
-    // assign curr_barrier_count    = $countones(curr_barrier_mask);
+    // assign b_count = $countones(b_mask);
 
-    assign curr_barrier_mask     = barrier_stall_mask[barrier_id][`NUM_WARPS-1:0];
+    assign b_mask = barrier_stall_mask[barrier_id][`NUM_WARPS-1:0];
-    assign reached_barrier_limit = curr_barrier_count == (num_warps);
+    assign reached_barrier_limit = b_count == (num_warps);
 
     assign wstall_this_cycle = wstall && (wstall_warp_num == warp_to_schedule); // Maybe bug
 
@@ -260,8 +260,8 @@ module VX_warp_sched (
 
     assign update_visible_active = (count_visible_active < 1) && !(stall || wstall_this_cycle || hazard || is_join);
 
-    wire[(1+32+`NUM_THREADS-1):0] q1 = {1'b1, 32'b0                   , thread_masks[split_warp_num]};
+    wire [(1+32+`NUM_THREADS-1):0] q1 = {1'b1, 32'b0                   , thread_masks[split_warp_num]};
-    wire[(1+32+`NUM_THREADS-1):0] q2 = {1'b0, split_save_pc           , split_later_mask};
+    wire [(1+32+`NUM_THREADS-1):0] q2 = {1'b0, split_save_pc           , split_later_mask};
 
     assign {join_fall, join_pc, join_tm} = d[join_warp_num];
 
@@ -285,7 +285,7 @@ module VX_warp_sched (
             .d    (d[curr_warp]),
             .q1   (q1),
             .q2   (q2)
-            );
+        );
     end
     endgenerate
 
@@ -318,9 +318,9 @@ module VX_warp_sched (
     VX_priority_encoder #(
         .N(`NUM_WARPS)
     ) choose_schedule (
-        .valids(use_active),
+        .valids (use_active),
-        .index (warp_to_schedule),
+        .index  (warp_to_schedule),
-        .found (schedule)
+        .found  (schedule)
     );
 
     // always @(*) begin

hw/rtl/cache/VX_bank.v

@@ -309,11 +309,11 @@ module VX_bank #(
 `DEBUG_END
     wire [31:0]        addr_st1       [STAGE_1_CYCLES-1:0];
 
-    integer p_stage;
+    integer i;
     always @(*) begin
         is_fill_in_pipe = 0;
-        for (p_stage = 0; p_stage < STAGE_1_CYCLES; p_stage=p_stage+1) begin
+        for (i = 0; i < STAGE_1_CYCLES; i=i+1) begin
-            if (is_fill_st1[p_stage]) begin
+            if (is_fill_st1[i]) begin
                 is_fill_in_pipe = 1;
             end
         end

hw/rtl/cache/VX_cache_core_req_bank_sel.v

@@ -50,15 +50,15 @@ module VX_cache_core_req_bank_sel #(
 );
 
     generate
-        integer curr_req;
+        integer i;
         always @(*) begin
             per_bank_valids = 0;
-            for (curr_req = 0; curr_req < NUM_REQUESTS; curr_req = curr_req + 1) begin
+            for (i = 0; i < NUM_REQUESTS; i = i + 1) begin
                 if (NUM_BANKS == 1) begin
                     // If there is only one bank, then only map requests to that bank
-                    per_bank_valids[0][curr_req] = core_req_valid[curr_req];
+                    per_bank_valids[0][i] = core_req_valid[i];
                 end else begin
-                    per_bank_valids[core_req_addr[curr_req][`BANK_SELECT_ADDR_RNG]][curr_req] = core_req_valid[curr_req];
+                    per_bank_valids[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i];
                 end
             end
         end

hw/rtl/cache/VX_cache_wb_sel_merge.v

@@ -91,43 +91,43 @@ module VX_cache_wb_sel_merge #(
     assign core_rsp_write    = per_bank_wb_wb[main_bank_index];
     assign core_rsp_warp_num = per_bank_wb_warp_num[main_bank_index];
 
-    integer this_bank;
+    integer i;
     generate
         always @(*) begin
-            core_rsp_valid    = 0;
+            core_rsp_valid = 0;
-            core_rsp_data = 0;
+            core_rsp_data  = 0;
-            core_rsp_pc       = 0;
+            core_rsp_pc    = 0;
             core_rsp_addr  = 0;
-            for (this_bank = 0; this_bank < NUM_BANKS; this_bank = this_bank + 1) begin
+            for (i = 0; i < NUM_BANKS; i = i + 1) begin
                 if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
                     if (found_bank
-                    && !core_rsp_valid[per_bank_wb_tid[this_bank]] 
+                    && !core_rsp_valid[per_bank_wb_tid[i]] 
-                    && per_bank_wb_valid[this_bank] 
+                    && per_bank_wb_valid[i] 
-                    && ((main_bank_index == `LOG2UP(NUM_BANKS)'(this_bank)) 
+                    && ((main_bank_index == `LOG2UP(NUM_BANKS)'(i)) 
-                    || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) begin
+                    || (per_bank_wb_tid[i] != per_bank_wb_tid[main_bank_index]))) begin
-                        core_rsp_valid[per_bank_wb_tid[this_bank]]    = 1;
+                        core_rsp_valid[per_bank_wb_tid[i]]    = 1;
-                        core_rsp_data[per_bank_wb_tid[this_bank]]     = per_bank_wb_data[this_bank];
+                        core_rsp_data[per_bank_wb_tid[i]]     = per_bank_wb_data[i];
-                        core_rsp_pc[per_bank_wb_tid[this_bank]]       = per_bank_wb_pc[this_bank];
+                        core_rsp_pc[per_bank_wb_tid[i]]       = per_bank_wb_pc[i];
-                        core_rsp_addr[per_bank_wb_tid[this_bank]]     = per_bank_wb_addr[this_bank];
+                        core_rsp_addr[per_bank_wb_tid[i]]     = per_bank_wb_addr[i];
-                        per_bank_wb_pop_unqual[this_bank]             = 1;
+                        per_bank_wb_pop_unqual[i]             = 1;
                     end else begin
-                        per_bank_wb_pop_unqual[this_bank]             = 0;
+                        per_bank_wb_pop_unqual[i]             = 0;
                     end
                 end else begin
-                    if (((main_bank_index == `LOG2UP(NUM_BANKS)'(this_bank))
+                    if (((main_bank_index == `LOG2UP(NUM_BANKS)'(i))
-                        || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index])) 
+                        || (per_bank_wb_tid[i] != per_bank_wb_tid[main_bank_index])) 
                     && found_bank 
-                    && !core_rsp_valid[per_bank_wb_tid[this_bank]] 
+                    && !core_rsp_valid[per_bank_wb_tid[i]] 
-                    && (per_bank_wb_valid[this_bank]) 
+                    && (per_bank_wb_valid[i]) 
-                    && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) 
+                    && (per_bank_wb_rd[i] == per_bank_wb_rd[main_bank_index]) 
-                    && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin
+                    && (per_bank_wb_warp_num[i] == per_bank_wb_warp_num[main_bank_index])) begin
-                        core_rsp_valid[per_bank_wb_tid[this_bank]]    = 1;
+                        core_rsp_valid[per_bank_wb_tid[i]]    = 1;
-                        core_rsp_data[per_bank_wb_tid[this_bank]]     = per_bank_wb_data[this_bank];
+                        core_rsp_data[per_bank_wb_tid[i]]     = per_bank_wb_data[i];
-                        core_rsp_pc[per_bank_wb_tid[this_bank]]       = per_bank_wb_pc[this_bank];
+                        core_rsp_pc[per_bank_wb_tid[i]]       = per_bank_wb_pc[i];
-                        core_rsp_addr[per_bank_wb_tid[this_bank]]     = per_bank_wb_addr[this_bank];
+                        core_rsp_addr[per_bank_wb_tid[i]]     = per_bank_wb_addr[i];
-                        per_bank_wb_pop_unqual[this_bank]             = 1;
+                        per_bank_wb_pop_unqual[i]             = 1;
                     end else begin
-                        per_bank_wb_pop_unqual[this_bank]             = 0;
+                        per_bank_wb_pop_unqual[i]             = 0;
                     end
                 end
             end

hw/rtl/libs/VX_byte_enabled_dual_port_ram.v

@@ -12,9 +12,6 @@ module VX_byte_enabled_dual_port_ram (
     output reg [`NUM_THREADS-1:0][31:0] q1,
 	output reg [`NUM_THREADS-1:0][31:0] q2
 );
-    // integer regi;
-    // integer threadi;
-
     // Thread   Byte  Bit
     logic [`NUM_THREADS-1:0][3:0][7:0] ram[31:0];
 
@@ -23,29 +20,20 @@ module VX_byte_enabled_dual_port_ram (
             //--
         end else begin
             if (we) begin
-                integer thread_ind;
+                integer t;
-                for (thread_ind = 0; thread_ind < `NUM_THREADS; thread_ind = thread_ind + 1) begin
+                for (t = 0; t < `NUM_THREADS; t = t + 1) begin
-                    if (be[thread_ind]) begin
+                    if (be[t]) begin
-                        ram[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
+                        ram[waddr][t][0] <= wdata[t][7:0];
-                        ram[waddr][thread_ind][1] <= wdata[thread_ind][15:8];
+                        ram[waddr][t][1] <= wdata[t][15:8];
-                        ram[waddr][thread_ind][2] <= wdata[thread_ind][23:16];
+                        ram[waddr][t][2] <= wdata[t][23:16];
-                        ram[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
+                        ram[waddr][t][3] <= wdata[t][31:24];
                     end
                 end
             end    
-            // $display("^^^^^^^^^^^^^^^^^^^^^^^");
-            // for (regi = 0; regi <= 31; regi = regi + 1) begin
-            //     for (threadi = 0; threadi < `NUM_THREADS; threadi = threadi + 1) begin
-            //         if (ram[regi][threadi] != 0) $display("$%d: %h",regi, ram[regi][threadi]);
-            //     end
-            // end
         end
     end
     
     assign q1 = ram[raddr1];
     assign q2 = ram[raddr2];
 
-    // assign q1 = (raddr1 == waddr && (we)) ? wdata : ram[raddr1];
-    // assign q2 = (raddr2 == waddr && (we)) ? wdata : ram[raddr2];
-
 endmodule

hw/syn/quartus/back_end/Makefile

@@ -0,0 +1,70 @@
+PROJECT = VX_back_end
+TOP_LEVEL_ENTITY = VX_back_end
+SRC_FILE = VX_back_end.v
+PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
+
+# Part, Family
+FAMILY = "Arria 10"
+DEVICE = 10AX115N3F40E2SG   
+
+# Executable Configuration
+SYN_ARGS = --parallel --read_settings_files=on
+FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
+ASM_ARGS =
+STA_ARGS = --do_report_timing
+
+# Build targets
+all: $(PROJECT).sta.rpt
+
+syn: $(PROJECT).syn.rpt
+
+fit: $(PROJECT).fit.rpt
+
+asm: $(PROJECT).asm.rpt
+
+sta: $(PROJECT).sta.rpt
+
+smart: smart.log
+
+# Target implementations
+STAMP = echo done >
+
+$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) 
+	quartus_syn $(PROJECT) $(SYN_ARGS)
+	$(STAMP) fit.chg
+
+$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
+	quartus_fit $(PROJECT) $(FIT_ARGS)
+	$(STAMP) asm.chg
+	$(STAMP) sta.chg
+
+$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
+	quartus_asm $(PROJECT) $(ASM_ARGS)
+
+$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
+	quartus_sta $(PROJECT)  $(STA_ARGS) 
+
+smart.log: $(PROJECT_FILES)
+	quartus_sh --determine_smart_action $(PROJECT) > smart.log
+
+# Project initialization
+$(PROJECT_FILES):
+	quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache"
+	
+syn.chg:
+	$(STAMP) syn.chg
+
+fit.chg:
+	$(STAMP) fit.chg
+
+sta.chg:
+	$(STAMP) sta.chg
+
+asm.chg:
+	$(STAMP) asm.chg
+
+program: $(PROJECT).sof
+	quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
+	
+clean:
+	rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

hw/syn/quartus/back_end/project.sdc

@@ -0,0 +1 @@
+create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

hw/syn/quartus/back_end/project.tcl

@@ -0,0 +1,41 @@
+load_package flow
+package require cmdline
+
+set options { \
+    { "project.arg" "" "Project name" } \
+    { "family.arg" "" "Device family name" } \
+    { "device.arg" "" "Device name" } \
+    { "top.arg" "" "Top level module" } \
+    { "sdc.arg" "" "Timing Design Constraints file" } \
+    { "src.arg" "" "Verilog source file" } \
+    { "inc.arg" "." "Include path" } \
+}
+
+array set opts [::cmdline::getoptions quartus(args) $options]
+
+project_new $opts(project) -overwrite
+
+set_global_assignment -name FAMILY $opts(family)
+set_global_assignment -name DEVICE $opts(device)
+set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
+set_global_assignment -name VERILOG_FILE $opts(src)
+set_global_assignment -name SEARCH_PATH $opts(inc)
+set_global_assignment -name SDC_FILE $opts(sdc)
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
+
+proc make_all_pins_virtual {} {
+    execute_module -tool map
+    set name_ids [get_names -filter * -node_type pin]
+    foreach_in_collection name_id $name_ids {        
+        set pin_name [get_name_info -info full_path $name_id]
+        post_message "Making VIRTUAL_PIN assignment to $pin_name"
+        set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
+    }
+    export_assignments
+}
+
+make_all_pins_virtual
+
+project_close

hw/syn/quartus/cache/Makefile

@@ -67,4 +67,4 @@ program: $(PROJECT).sof
 	quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
 	
 clean:
-	rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
+	rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

hw/syn/quartus/dmem_ctrl/Makefile

@@ -0,0 +1,70 @@
+PROJECT = VX_dmem_ctrl
+TOP_LEVEL_ENTITY = VX_dmem_ctrl
+SRC_FILE = VX_dmem_ctrl.v
+PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
+
+# Part, Family
+FAMILY = "Arria 10"
+DEVICE = 10AX115N3F40E2SG   
+
+# Executable Configuration
+SYN_ARGS = --parallel --read_settings_files=on
+FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
+ASM_ARGS =
+STA_ARGS = --do_report_timing
+
+# Build targets
+all: $(PROJECT).sta.rpt
+
+syn: $(PROJECT).syn.rpt
+
+fit: $(PROJECT).fit.rpt
+
+asm: $(PROJECT).asm.rpt
+
+sta: $(PROJECT).sta.rpt
+
+smart: smart.log
+
+# Target implementations
+STAMP = echo done >
+
+$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) 
+	quartus_syn $(PROJECT) $(SYN_ARGS)
+	$(STAMP) fit.chg
+
+$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
+	quartus_fit $(PROJECT) $(FIT_ARGS)
+	$(STAMP) asm.chg
+	$(STAMP) sta.chg
+
+$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
+	quartus_asm $(PROJECT) $(ASM_ARGS)
+
+$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
+	quartus_sta $(PROJECT)  $(STA_ARGS) 
+
+smart.log: $(PROJECT_FILES)
+	quartus_sh --determine_smart_action $(PROJECT) > smart.log
+
+# Project initialization
+$(PROJECT_FILES):
+	quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache"
+	
+syn.chg:
+	$(STAMP) syn.chg
+
+fit.chg:
+	$(STAMP) fit.chg
+
+sta.chg:
+	$(STAMP) sta.chg
+
+asm.chg:
+	$(STAMP) asm.chg
+
+program: $(PROJECT).sof
+	quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
+	
+clean:
+	rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

hw/syn/quartus/dmem_ctrl/project.sdc

@@ -0,0 +1 @@
+create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

hw/syn/quartus/dmem_ctrl/project.tcl

@@ -0,0 +1,41 @@
+load_package flow
+package require cmdline
+
+set options { \
+    { "project.arg" "" "Project name" } \
+    { "family.arg" "" "Device family name" } \
+    { "device.arg" "" "Device name" } \
+    { "top.arg" "" "Top level module" } \
+    { "sdc.arg" "" "Timing Design Constraints file" } \
+    { "src.arg" "" "Verilog source file" } \
+    { "inc.arg" "." "Include path" } \
+}
+
+array set opts [::cmdline::getoptions quartus(args) $options]
+
+project_new $opts(project) -overwrite
+
+set_global_assignment -name FAMILY $opts(family)
+set_global_assignment -name DEVICE $opts(device)
+set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
+set_global_assignment -name VERILOG_FILE $opts(src)
+set_global_assignment -name SEARCH_PATH $opts(inc)
+set_global_assignment -name SDC_FILE $opts(sdc)
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
+
+proc make_all_pins_virtual {} {
+    execute_module -tool map
+    set name_ids [get_names -filter * -node_type pin]
+    foreach_in_collection name_id $name_ids {        
+        set pin_name [get_name_info -info full_path $name_id]
+        post_message "Making VIRTUAL_PIN assignment to $pin_name"
+        set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
+    }
+    export_assignments
+}
+
+make_all_pins_virtual
+
+project_close

hw/syn/quartus/front_end/Makefile

@@ -0,0 +1,70 @@
+PROJECT = VX_front_end
+TOP_LEVEL_ENTITY = VX_front_end
+SRC_FILE = VX_front_end.v
+PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
+
+# Part, Family
+FAMILY = "Arria 10"
+DEVICE = 10AX115N3F40E2SG   
+
+# Executable Configuration
+SYN_ARGS = --parallel --read_settings_files=on
+FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
+ASM_ARGS =
+STA_ARGS = --do_report_timing
+
+# Build targets
+all: $(PROJECT).sta.rpt
+
+syn: $(PROJECT).syn.rpt
+
+fit: $(PROJECT).fit.rpt
+
+asm: $(PROJECT).asm.rpt
+
+sta: $(PROJECT).sta.rpt
+
+smart: smart.log
+
+# Target implementations
+STAMP = echo done >
+
+$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) 
+	quartus_syn $(PROJECT) $(SYN_ARGS)
+	$(STAMP) fit.chg
+
+$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
+	quartus_fit $(PROJECT) $(FIT_ARGS)
+	$(STAMP) asm.chg
+	$(STAMP) sta.chg
+
+$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
+	quartus_asm $(PROJECT) $(ASM_ARGS)
+
+$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
+	quartus_sta $(PROJECT)  $(STA_ARGS) 
+
+smart.log: $(PROJECT_FILES)
+	quartus_sh --determine_smart_action $(PROJECT) > smart.log
+
+# Project initialization
+$(PROJECT_FILES):
+	quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache"
+	
+syn.chg:
+	$(STAMP) syn.chg
+
+fit.chg:
+	$(STAMP) fit.chg
+
+sta.chg:
+	$(STAMP) sta.chg
+
+asm.chg:
+	$(STAMP) asm.chg
+
+program: $(PROJECT).sof
+	quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
+	
+clean:
+	rm -rf bin *.rpt *.chg *.qsf *.qpf  *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

hw/syn/quartus/front_end/project.sdc

@@ -0,0 +1 @@
+create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

hw/syn/quartus/front_end/project.tcl

@@ -0,0 +1,41 @@
+load_package flow
+package require cmdline
+
+set options { \
+    { "project.arg" "" "Project name" } \
+    { "family.arg" "" "Device family name" } \
+    { "device.arg" "" "Device name" } \
+    { "top.arg" "" "Top level module" } \
+    { "sdc.arg" "" "Timing Design Constraints file" } \
+    { "src.arg" "" "Verilog source file" } \
+    { "inc.arg" "." "Include path" } \
+}
+
+array set opts [::cmdline::getoptions quartus(args) $options]
+
+project_new $opts(project) -overwrite
+
+set_global_assignment -name FAMILY $opts(family)
+set_global_assignment -name DEVICE $opts(device)
+set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
+set_global_assignment -name VERILOG_FILE $opts(src)
+set_global_assignment -name SEARCH_PATH $opts(inc)
+set_global_assignment -name SDC_FILE $opts(sdc)
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
+
+proc make_all_pins_virtual {} {
+    execute_module -tool map
+    set name_ids [get_names -filter * -node_type pin]
+    foreach_in_collection name_id $name_ids {        
+        set pin_name [get_name_info -info full_path $name_id]
+        post_message "Making VIRTUAL_PIN assignment to $pin_name"
+        set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
+    }
+    export_assignments
+}
+
+make_all_pins_virtual
+
+project_close

hw/syn/quartus/scheduler/Makefile

@@ -0,0 +1,70 @@
+PROJECT = VX_scheduler
+TOP_LEVEL_ENTITY = VX_scheduler
+SRC_FILE = VX_scheduler.v
+PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
+
+# Part, Family
+FAMILY = "Arria 10"
+DEVICE = 10AX115N3F40E2SG   
+
+# Executable Configuration
+SYN_ARGS = --parallel --read_settings_files=on
+FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
+ASM_ARGS =
+STA_ARGS = --do_report_timing
+
+# Build targets
+all: $(PROJECT).sta.rpt
+
+syn: $(PROJECT).syn.rpt
+
+fit: $(PROJECT).fit.rpt
+
+asm: $(PROJECT).asm.rpt
+
+sta: $(PROJECT).sta.rpt
+
+smart: smart.log
+
+# Target implementations
+STAMP = echo done >
+
+$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) 
+	quartus_syn $(PROJECT) $(SYN_ARGS)
+	$(STAMP) fit.chg
+
+$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
+	quartus_fit $(PROJECT) $(FIT_ARGS)
+	$(STAMP) asm.chg
+	$(STAMP) sta.chg
+
+$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
+	quartus_asm $(PROJECT) $(ASM_ARGS)
+
+$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
+	quartus_sta $(PROJECT)  $(STA_ARGS) 
+
+smart.log: $(PROJECT_FILES)
+	quartus_sh --determine_smart_action $(PROJECT) > smart.log
+
+# Project initialization
+$(PROJECT_FILES):
+	quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache"
+	
+syn.chg:
+	$(STAMP) syn.chg
+
+fit.chg:
+	$(STAMP) fit.chg
+
+sta.chg:
+	$(STAMP) sta.chg
+
+asm.chg:
+	$(STAMP) asm.chg
+
+program: $(PROJECT).sof
+	quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
+	
+clean:
+	rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

hw/syn/quartus/scheduler/project.sdc

@@ -0,0 +1 @@
+create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

hw/syn/quartus/scheduler/project.tcl

@@ -0,0 +1,41 @@
+load_package flow
+package require cmdline
+
+set options { \
+    { "project.arg" "" "Project name" } \
+    { "family.arg" "" "Device family name" } \
+    { "device.arg" "" "Device name" } \
+    { "top.arg" "" "Top level module" } \
+    { "sdc.arg" "" "Timing Design Constraints file" } \
+    { "src.arg" "" "Verilog source file" } \
+    { "inc.arg" "." "Include path" } \
+}
+
+array set opts [::cmdline::getoptions quartus(args) $options]
+
+project_new $opts(project) -overwrite
+
+set_global_assignment -name FAMILY $opts(family)
+set_global_assignment -name DEVICE $opts(device)
+set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
+set_global_assignment -name VERILOG_FILE $opts(src)
+set_global_assignment -name SEARCH_PATH $opts(inc)
+set_global_assignment -name SDC_FILE $opts(sdc)
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
+
+proc make_all_pins_virtual {} {
+    execute_module -tool map
+    set name_ids [get_names -filter * -node_type pin]
+    foreach_in_collection name_id $name_ids {        
+        set pin_name [get_name_info -info full_path $name_id]
+        post_message "Making VIRTUAL_PIN assignment to $pin_name"
+        set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
+    }
+    export_assignments
+}
+
+make_all_pins_virtual
+
+project_close

hw/syn/quartus/top/Makefile

@@ -67,4 +67,4 @@ program: $(PROJECT).sof
 	quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
 	
 clean:
-	rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
+	rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox