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tex_unit memory partial

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Blaise Tine
2021-03-22 10:25:17 -04:00
parent 0909ad3201
commit f499ce6c95
7 changed files with 271 additions and 335 deletions
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14
hw/rtl/VX_define.vh
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@@ -281,13 +281,19 @@
// Word size in bytes
`define DWORD_SIZE 4
// TAG sharing enable
`define DCORE_TAG_ID_BITS `LOG2UP(`LSUQ_SIZE)
// TAG sharing enable
`define LSUQ_ADDR_BITS `LOG2UP(`LSUQ_SIZE)
`ifdef EXT_TEX_ENABLE
`define DCORE_TAG_ID_BITS (`LSUQ_ADDR_BITS + 2)
`else
`define DCORE_TAG_ID_BITS `LSUQ_ADDR_BITS
`endif
// Core request tag bits
`ifdef EXT_TEX_ENABLE
`define LSU_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `DCORE_TAG_ID_BITS)
`define DCORE_TAG_WIDTH (`LSU_TAG_WIDTH+1)
`define LSU_DACHE_TAG_BITS (`DBG_CACHE_REQ_MDATAW + `LSUQ_ADDR_BITS)
`define TEX_DACHE_TAG_BITS (`DBG_CACHE_REQ_MDATAW + 2 + `LSUQ_ADDR_BITS)
`define DCORE_TAG_WIDTH (`MAX(`LSU_DACHE_TAG_BITS, `TEX_DACHE_TAG_BITS) + 1)
`else
`define DCORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `DCORE_TAG_ID_BITS)
`endif