Texture Instruction - Fixed Color
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@@ -11,6 +11,7 @@ module VX_writeback #(
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VX_commit_if ld_commit_if,
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VX_commit_if csr_commit_if,
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VX_commit_if fpu_commit_if,
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VX_commit_if gpu_commit_if,
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// outputs
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VX_writeback_if writeback_if
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@@ -19,6 +20,7 @@ module VX_writeback #(
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wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb;
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wire csr_valid = csr_commit_if.valid && csr_commit_if.wb;
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wire alu_valid = alu_commit_if.valid && alu_commit_if.wb;
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wire gpu_valid = gpu_commit_if.valid && gpu_commit_if.wb;
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wire wb_valid;
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wire [`NW_BITS-1:0] wb_wid;
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@@ -31,37 +33,44 @@ module VX_writeback #(
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assign wb_valid = ld_valid |
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fpu_valid |
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csr_valid |
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alu_valid;
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alu_valid |
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gpu_valid;
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assign wb_wid = ld_valid ? ld_commit_if.wid :
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fpu_valid ? fpu_commit_if.wid :
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csr_valid ? csr_commit_if.wid :
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/*alu_valid ?*/ alu_commit_if.wid;
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alu_valid ? alu_commit_if.wid :
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/*gpu_valid*/ gpu_commit_if.wid;
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assign wb_PC = ld_valid ? ld_commit_if.PC :
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fpu_valid ? fpu_commit_if.PC :
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csr_valid ? csr_commit_if.PC :
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/*alu_valid ?*/ alu_commit_if.PC;
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alu_valid ? alu_commit_if.PC :
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/*gpu_valid*/ gpu_commit_if.PC;
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assign wb_tmask = ld_valid ? ld_commit_if.tmask :
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fpu_valid ? fpu_commit_if.tmask :
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csr_valid ? csr_commit_if.tmask :
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/*alu_valid ?*/ alu_commit_if.tmask;
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alu_valid ? alu_commit_if.tmask :
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/*gpu_valid*/ gpu_commit_if.tmask;
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assign wb_rd = ld_valid ? ld_commit_if.rd :
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fpu_valid ? fpu_commit_if.rd :
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csr_valid ? csr_commit_if.rd :
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/*alu_valid ?*/ alu_commit_if.rd;
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alu_valid ? alu_commit_if.rd :
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/*gpu_valid*/ gpu_commit_if.rd;
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assign wb_data = ld_valid ? ld_commit_if.data :
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fpu_valid ? fpu_commit_if.data :
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csr_valid ? csr_commit_if.data :
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/*alu_valid ?*/ alu_commit_if.data;
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alu_valid ? alu_commit_if.data :
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/*gpu_valid*/ gpu_commit_if.data;
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assign wb_eop = ld_valid ? ld_commit_if.eop :
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fpu_valid ? fpu_commit_if.eop :
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csr_valid ? csr_commit_if.eop :
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/*alu_valid ?*/ alu_commit_if.eop;
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alu_valid ? alu_commit_if.eop :
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/*gpu_valid*/ gpu_commit_if.eop;
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wire stall = ~writeback_if.ready && writeback_if.valid;
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@@ -79,7 +88,9 @@ module VX_writeback #(
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assign ld_commit_if.ready = !stall;
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assign fpu_commit_if.ready = !stall && !ld_valid;
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assign csr_commit_if.ready = !stall && !ld_valid && !fpu_valid;
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assign alu_commit_if.ready = !stall && !ld_valid && !fpu_valid && !csr_valid;
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assign alu_commit_if.ready = !stall && !ld_valid && !fpu_valid && !csr_valid;
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// if not TEX instruction, no writeback and commit is ready
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assign gpu_commit_if.ready = (!stall && !ld_valid && !fpu_valid && !csr_valid && !alu_valid) || !gpu_commit_if.wb ;
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// special workaround to get RISC-V tests Pass/Fail status
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reg [31:0] last_wb_value [`NUM_REGS-1:0] /* verilator public */;
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