afu reset fix

driver/common/vx_utils.cpp

@@ -338,7 +338,6 @@ extern int vx_dump_perf(vx_device_h device, FILE* stream) {
   fprintf(stream, "PERF: dram requests=%ld (reads=%ld, writes=%ld)\n", (dram_reads + dram_writes), dram_reads, dram_writes);
   fprintf(stream, "PERF: dram stalls=%ld (utilization=%d%%)\n", dram_stalls, dram_utilization);
   fprintf(stream, "PERF: dram average latency=%d cycles\n", dram_avg_lat);
-  fprintf(stream, "PERF: dram bandwith=%d cycles\n", dram_avg_lat);
 #endif
 
   return ret;

hw/rtl/afu/vortex_afu.sv

@@ -126,7 +126,7 @@ wire        vx_csr_io_rsp_ready;
 wire        vx_busy;
 
 reg vx_reset;
-reg vx_enabled;
+reg vx_dram_en;
 
 // CMD variables //////////////////////////////////////////////////////////////
 
@@ -179,7 +179,8 @@ wire[$bits(cp2af_sRxPort.c0.hdr.mdata)-1:0] cp2af_sRxPort_c0_hdr_mdata = cp2af_s
 `DEBUG_END
 */
 
-wire [2:0] cmd_type = (cp2af_sRxPort.c0.mmioWrValid && (MMIO_CMD_TYPE == mmio_hdr.address)) ? 3'(cp2af_sRxPort.c0.data) : 3'h0;
+wire [2:0] cmd_type = (cp2af_sRxPort.c0.mmioWrValid 
+                    && (MMIO_CMD_TYPE == mmio_hdr.address)) ? 3'(cp2af_sRxPort.c0.data) : 3'h0;
 
 `ifdef SCOPE
 reg scope_start;
@@ -187,16 +188,16 @@ reg scope_start;
 
 // disable assertions until full reset
 `ifndef VERILATOR
-reg [$clog2(RESET_DELAY+1)-1:0] reset_ctr;
+reg [$clog2(RESET_DELAY+1)-1:0] assert_delay_ctr;
 initial begin
   $assertoff;  
 end
 always @(posedge clk) begin
   if (reset) begin
-    reset_ctr <= 0;
+    assert_delay_ctr <= 0;
   end else begin
-    reset_ctr <= reset_ctr + 1;
+    assert_delay_ctr <= assert_delay_ctr + 1;
-    if (reset_ctr == RESET_DELAY) begin
+    if (assert_delay_ctr == RESET_DELAY) begin
       $asserton; // enable assertions
     end
   end
@@ -349,11 +350,8 @@ always @(posedge clk) begin
   if (reset) begin
     state      <= STATE_IDLE;    
     vx_reset   <= 0;    
-    vx_enabled <= 0;
+    vx_dram_en <= 0;
   end else begin
-    
-    vx_reset <= 0;
-
     case (state)
       STATE_IDLE: begin             
         case (cmd_type)
@@ -373,8 +371,7 @@ always @(posedge clk) begin
           `ifdef DBG_PRINT_OPAE
             $display("%t: STATE START", $time);
           `endif
-            vx_reset   <= 1;
+            vx_reset <= 1;            
-            vx_enabled <= 1;
             state <= STATE_START;                    
           end
           CMD_CSR_READ: begin
@@ -415,12 +412,16 @@ always @(posedge clk) begin
 
       STATE_START: begin 
         // vortex reset cycles
-        if (vx_reset_ctr == $bits(vx_reset_ctr)'(RESET_DELAY))
+        if (vx_reset_ctr == $bits(vx_reset_ctr)'(RESET_DELAY)) begin
+          vx_reset   <= 0;  
+          vx_dram_en <= 1;
           state <= STATE_RUN;
+        end
       end
 
       STATE_RUN: begin
         if (cmd_run_done) begin
+          vx_dram_en <= 0;
           state <= STATE_IDLE;
         `ifdef DBG_PRINT_OPAE
           $display("%t: STATE IDLE", $time);
@@ -508,7 +509,7 @@ assign cci_dram_req_tag    = AVS_REQ_TAGW'(0);
 
 //--
 
-assign vx_dram_req_valid_qual = vx_dram_req_valid && vx_enabled;
+assign vx_dram_req_valid_qual = vx_dram_req_valid && vx_dram_en;
 
 assign vx_dram_req_addr_qual = vx_dram_req_addr[`VX_DRAM_ADDR_WIDTH-1:`VX_DRAM_ADDR_WIDTH-DRAM_ADDR_WIDTH];
 
@@ -816,9 +817,9 @@ assign cmd_read_done = (0 == cci_wr_req_ctr) && cci_pending_writes_empty;
 always @(posedge clk) 
 begin
   if (reset) begin
-    cci_wr_req_addr     <= 0;
+    cci_wr_req_addr        <= 0;
-    cci_wr_req_ctr      <= 0;
+    cci_wr_req_ctr         <= 0;
-    cci_dram_rd_req_ctr <= 0;
+    cci_dram_rd_req_ctr    <= 0;
     cci_dram_rd_req_addr_r <= 0;
   end
   else begin    

hw/scripts/scope.py

@@ -147,6 +147,7 @@ def remove_comments(text):
 def add_macro(name, args, value):
     macro = (name, args, value)
     macros.append(macro)
+    '''
     if not args is None:
         print("*** token: " + name + "(", end='')        
         for i in range(len(args)):
@@ -156,6 +157,7 @@ def add_macro(name, args, value):
         print(")=" + value)
     else:
         print("*** token: " + name + "=" + value)
+    '''
 
 def find_macro(name):
     for macro in macros:
@@ -273,7 +275,7 @@ def expand_text(text, params):
 def parse_include(filename, nesting):    
     if nesting > 99:
         raise Exception("include recursion!")    
-    print("*** parsing '" + filename + "'...")    
+    #print("*** parsing '" + filename + "'...")    
     content = None
     with open(filename, "r") as f:        
         content = f.read()
@@ -306,7 +308,7 @@ def parse_include(filename, nesting):
             elif key == '"elsif':
                 br_stack.pop()
             br_stack.append(taken)
-            print("*** " + key + "(" + cond + ") => " + str(taken))
+            #print("*** " + key + "(" + cond + ") => " + str(taken))
             continue  
         # parse endif
         m = re.match(vl_endif_re, line)
@@ -315,7 +317,7 @@ def parse_include(filename, nesting):
             top = br_stack.pop()
             if key == 'else':                
                 br_stack.append(not top)
-            print("*** " + key)
+            #print("*** " + key)
             continue
         # skip disabled blocks
         if not all(br_stack):
@@ -360,7 +362,7 @@ def parse_includes(includes):
 
 def load_include_dirs(dirs):
     for dir in dirs:
-        print("*** include dir: " + dir)
+        #print("*** include dir: " + dir)
         include_dirs.append(dir)
 
 def load_defines(defines):
@@ -573,7 +575,7 @@ def gen_vl_header(file, modules, taps):
             skey_list = key.split(',')
             _taps = taps[key]
             for skey in skey_list:
-                print('processing node: ' + skey + ' ...')
+                #print('*** processing node: ' + skey + ' ...')
                 paths = skey.strip().split('/')
                 ntype = paths.pop(0)
                 curtaps = visit_path(alltaps, ports, ntype, paths, modules, _taps)