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rtl refactoring

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This commit is contained in:
Blaise Tine
2020-05-04 20:12:05 -04:00
parent 69f607b73e
commit f142afac80
39 changed files with 31067 additions and 31607 deletions
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13
hw/rtl/interfaces/VX_cache_core_req_if.v
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@@ -4,17 +4,18 @@
`include "../cache/VX_cache_config.vh"
interface VX_cache_core_req_if #(
parameter NUM_REQUESTS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
parameter NUM_REQUESTS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1,
parameter CORE_TAG_ID_BITS = 0
) ();
wire [NUM_REQUESTS-1:0] core_req_valid;
wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] core_req_read;
wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] core_req_write;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_read;
wire [NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] core_req_write;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data;
wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag;
wire core_req_ready;
endinterface

9
hw/rtl/interfaces/VX_cache_core_rsp_if.v
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@@ -4,14 +4,15 @@
`include "../cache/VX_cache_config.vh"
interface VX_cache_core_rsp_if #(
parameter NUM_REQUESTS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
parameter NUM_REQUESTS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1,
parameter CORE_TAG_ID_BITS = 0
) ();
wire [NUM_REQUESTS-1:0] core_rsp_valid;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data;
wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag;
wire core_rsp_ready;
endinterface

4
hw/rtl/interfaces/VX_frE_to_bckE_req_if.v
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@@ -16,8 +16,8 @@ interface VX_frE_to_bckE_req_if ();
wire [1:0] wb;
wire rs2_src;
wire [31:0] itype_immed;
wire [`WORD_SEL_BITS-1:0] mem_read;
wire [`WORD_SEL_BITS-1:0] mem_write;
wire [`BYTE_EN_BITS-1:0] mem_read;
wire [`BYTE_EN_BITS-1:0] mem_write;
wire [2:0] branch_type;
wire [19:0] upper_immed;
wire [31:0] curr_PC;

4
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -12,8 +12,8 @@ interface VX_lsu_req_if ();
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_address; // A reg data
wire [31:0] offset; // itype_immed
wire [`WORD_SEL_BITS-1:0] mem_read;
wire [`WORD_SEL_BITS-1:0] mem_write;
wire [`BYTE_EN_BITS-1:0] mem_read;
wire [`BYTE_EN_BITS-1:0] mem_write;
wire [4:0] rd; // dest register
wire [1:0] wb; //