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rtl refactoring

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This commit is contained in:
Blaise Tine
2020-05-04 20:12:05 -04:00
parent 69f607b73e
commit f142afac80
39 changed files with 31067 additions and 31607 deletions
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4
hw/rtl/VX_scheduler.v
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@@ -25,8 +25,8 @@ module VX_scheduler (
wire rs2_rename = rename_table[bckE_req_if.warp_num][bckE_req_if.rs2] != 0;
wire rd_rename = rename_table[bckE_req_if.warp_num][bckE_req_if.rd ] != 0;
wire is_store = (bckE_req_if.mem_write != `WORD_SEL_NO);
wire is_load = (bckE_req_if.mem_read != `WORD_SEL_NO);
wire is_store = (bckE_req_if.mem_write != `BYTE_EN_NO);
wire is_load = (bckE_req_if.mem_read != `BYTE_EN_NO);
// classify our next instruction.
wire is_mem = is_store || is_load;