fixed Verilator warnings
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@@ -19,8 +19,6 @@ module VX_stream_arbiter #(
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output wire [LANES-1:0][DATAW-1:0] data_out,
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input wire [LANES-1:0] ready_out
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);
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localparam LOG_NUM_REQS = $clog2(NUM_REQS);
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if (NUM_REQS > 1) begin
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wire sel_valid;
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