fixed Verilator warnings

2021-08-13 05:52:43 -04:00
parent 4976a8c4f2
commit f12be56d7c
8 changed files with 35 additions and 41 deletions
--- a/hw/rtl/cache/VX_bank.v
+++ b/hw/rtl/cache/VX_bank.v
@@ -379,7 +379,6 @@ module VX_bank #(
        .WORD_SIZE          (WORD_SIZE),
        .NUM_REQS           (NUM_REQS),
        .MSHR_SIZE          (MSHR_SIZE),
-        .ALM_FULL           (MSHR_SIZE-2),
        .CORE_TAG_WIDTH     (CORE_TAG_WIDTH)
    ) miss_resrv (
        .clk                (clk),
--- a/hw/rtl/cache/VX_miss_resrv.v
+++ b/hw/rtl/cache/VX_miss_resrv.v
@@ -16,8 +16,7 @@ module VX_miss_resrv #(
    // Size of a word in bytes
    parameter WORD_SIZE         = 1, 
    // Miss Reserv Queue Knob
-    parameter MSHR_SIZE         = 1, 
-    parameter ALM_FULL          = (MSHR_SIZE-1),
+    parameter MSHR_SIZE         = 1,
    // core request tag size
    parameter CORE_TAG_WIDTH    = 1,