Generate define overrides based on env vars for C and Verilog.

gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.

.gitignore

@@ -4,5 +4,6 @@
 ./rtl/modelsim/*.vcd
 *.vcd
 .*
+!.gitignore
 *.pyc
-__pycache__
+__pycache__