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Added tests to commit. 64 bit simx still not working

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This commit is contained in:
Santosh Raghav Srivatsan
2021-12-01 02:44:14 -05:00
parent 28ab94e925
commit f0dc04ad04
14 changed files with 284 additions and 111 deletions
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54
sim/simX/decode.cpp
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@@ -46,10 +46,10 @@ static const std::unordered_map<int, struct InstTableEntry_t> sc_instTable = {
};
static const char* op_string(const Instr &instr) {
Word func3 = instr.getFunc3();
Word func7 = instr.getFunc7();
Word rs2 = instr.getRSrc(1);
Word imm = instr.getImm();
HalfWord func3 = instr.getFunc3();
HalfWord func7 = instr.getFunc7();
HalfWord rs2 = instr.getRSrc(1);
HalfWord imm = instr.getImm();
switch (instr.getOpcode()) {
case Opcode::NOP: return "NOP";
case Opcode::LUI_INST: return "LUI";
@@ -273,7 +273,8 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
}
Decoder::Decoder(const ArchDef &arch) {
inst_s_ = arch.wsize() * 8;
// simx64
inst_s_ = arch.wsize() * 4;
opcode_s_ = 7;
reg_s_ = 5;
func2_s_ = 2;
@@ -307,20 +308,21 @@ Decoder::Decoder(const ArchDef &arch) {
v_imm_mask_ = 0x7ff;
}
std::shared_ptr<Instr> Decoder::decode(uint32_t code, uint32_t PC) {
// simx64
std::shared_ptr<Instr> Decoder::decode(HalfWord code, HalfWord PC) {
auto instr = std::make_shared<Instr>();
Opcode op = (Opcode)((code >> shift_opcode_) & opcode_mask_);
instr->setOpcode(op);
Word func3 = (code >> shift_func3_) & func3_mask_;
Word func6 = (code >> shift_func6_) & func6_mask_;
Word func7 = (code >> shift_func7_) & func7_mask_;
HalfWord func3 = (code >> shift_func3_) & func3_mask_;
HalfWord func6 = (code >> shift_func6_) & func6_mask_;
HalfWord func7 = (code >> shift_func7_) & func7_mask_;
// simx64
long rd = (code >> shift_rd_) & reg_mask_;
long rs1 = (code >> shift_rs1_) & reg_mask_;
long rs2 = (code >> shift_rs2_) & reg_mask_;
long rs3 = (code >> shift_rs3_) & reg_mask_;
int rd = (code >> shift_rd_) & reg_mask_;
int rs1 = (code >> shift_rs1_) & reg_mask_;
int rs2 = (code >> shift_rs2_) & reg_mask_;
int rs3 = (code >> shift_rs3_) & reg_mask_;
auto op_it = sc_instTable.find(op);
if (op_it == sc_instTable.end()) {
@@ -392,7 +394,7 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code, uint32_t PC) {
instr->setSrcReg(rs2);
}
instr->setFunc3(func3);
Word imeed = (func7 << reg_s_) | rd;
HalfWord imeed = (func7 << reg_s_) | rd;
instr->setImm(signExt(imeed, 12, s_imm_mask_));
} break;
@@ -400,11 +402,11 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code, uint32_t PC) {
instr->setSrcReg(rs1);
instr->setSrcReg(rs2);
instr->setFunc3(func3);
Word bit_11 = rd & 0x1;
Word bits_4_1 = rd >> 1;
Word bit_10_5 = func7 & 0x3f;
Word bit_12 = func7 >> 6;
Word imeed = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
HalfWord bit_11 = rd & 0x1;
HalfWord bits_4_1 = rd >> 1;
HalfWord bit_10_5 = func7 & 0x3f;
HalfWord bit_12 = func7 >> 6;
HalfWord imeed = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
instr->setImm(signExt(imeed, 13, b_imm_mask_));
} break;
@@ -415,12 +417,12 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code, uint32_t PC) {
case InstType::J_TYPE: {
instr->setDestReg(rd);
Word unordered = code >> shift_func3_;
Word bits_19_12 = unordered & 0xff;
Word bit_11 = (unordered >> 8) & 0x1;
Word bits_10_1 = (unordered >> 9) & 0x3ff;
Word bit_20 = (unordered >> 19) & 0x1;
Word imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
HalfWord unordered = code >> shift_func3_;
HalfWord bits_19_12 = unordered & 0xff;
HalfWord bit_11 = (unordered >> 8) & 0x1;
HalfWord bits_10_1 = (unordered >> 9) & 0x3ff;
HalfWord bit_20 = (unordered >> 19) & 0x1;
HalfWord imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
if (bit_20) {
imeed |= ~j_imm_mask_;
}
@@ -436,7 +438,7 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code, uint32_t PC) {
if (func3 == 7) {
instr->setImm(!(code >> shift_vset_));
if (instr->getImm()) {
Word immed = (code >> shift_rs2_) & v_imm_mask_;
HalfWord immed = (code >> shift_rs2_) & v_imm_mask_;
instr->setImm(immed);
instr->setVlmul(immed & 0x3);
instr->setVediv((immed >> 4) & 0x3);