wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

floating point support fixes + riscv-tests update

Browse Source
This commit is contained in:
Blaise Tine
2020-07-28 02:19:11 -04:00
parent e0a9089647
commit f01afcc5cd
338 changed files with 34269 additions and 36690 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
hw/simulate/simulator.cpp
View File

@@ -255,14 +255,11 @@ void Simulator::run() {
this->wait(5);
}
int Simulator::get_status(int reg) {
// check riscv-tests PASSED/FAILED status
#if (NUM_CLUSTERS == 1 && NUM_CORES == 1)
return (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_data_wb[reg];
#elif (NUM_CLUSTERS == 1)
return (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_data_wb[reg];
int Simulator::get_last_wb_value(int reg) {
#if (NUM_CLUSTERS == 1)
return (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
#else
return (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_data_wb[reg];
return (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
#endif
}

2
hw/simulate/simulator.h
View File

@@ -44,7 +44,7 @@ public:
void attach_ram(RAM* ram);
void run();
int get_status(int reg);
int get_last_wb_value(int reg);
void print_stats(std::ostream& out);
private:

127
hw/simulate/testbench.cpp
View File

@@ -9,70 +9,70 @@ int main(int argc, char **argv)
#ifdef ALL_TESTS
bool passed = true;
std::string tests[] = {/*
"../../../benchmarks/riscv_tests/rv32ui-p-add.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-addi.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-and.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-andi.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-auipc.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-beq.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-bge.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-bgeu.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-blt.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-bltu.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-bne.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-jal.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-jalr.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-lb.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-lbu.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-lh.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-lhu.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-lui.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-lw.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-or.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-ori.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sb.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sh.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-simple.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sll.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-slli.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-slt.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-slti.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sltiu.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sltu.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sra.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-srai.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-srl.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-srli.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sub.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sw.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-xor.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-xori.hex",
std::string tests[] = {
"../../../benchmarks/riscv_tests/isa/rv32ui-p-add.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-addi.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-and.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-andi.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-auipc.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-beq.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bge.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bgeu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-blt.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bltu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bne.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-jal.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-jalr.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lb.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lbu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lh.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lhu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lui.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lw.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-or.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-ori.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sb.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sh.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-simple.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sll.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-slli.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-slt.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-slti.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sltiu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sltu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sra.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-srai.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-srl.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-srli.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sub.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sw.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-xor.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-xori.hex",
#ifdef EXT_M_ENABLE
"../../../benchmarks/riscv_tests/rv32um-p-div.hex",
"../../../benchmarks/riscv_tests/rv32um-p-divu.hex",
"../../../benchmarks/riscv_tests/rv32um-p-mul.hex",
"../../../benchmarks/riscv_tests/rv32um-p-mulh.hex",
"../../../benchmarks/riscv_tests/rv32um-p-mulhsu.hex",
"../../../benchmarks/riscv_tests/rv32um-p-mulhu.hex",
"../../../benchmarks/riscv_tests/rv32um-p-rem.hex",
"../../../benchmarks/riscv_tests/rv32um-p-remu.hex",
#endif*/
"../../../benchmarks/riscv_tests/isa/rv32um-p-div.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-divu.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mul.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mulh.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mulhsu.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mulhu.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-rem.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-remu.hex",
#endif
};
std::string tests_fp[] = {
#ifdef EXT_F_ENABLE
//"../../../benchmarks/riscv_tests/rv32uf-p-fadd.hex",
//"../../../benchmarks/riscv_tests/rv32uf-p-fdiv.hex",
//"../../../benchmarks/riscv_tests/rv32uf-p-fmadd.hex",
//"../../../benchmarks/riscv_tests/rv32uf-p-fmin.hex",
//"../../../benchmarks/riscv_tests/rv32uf-p-fcmp.hex",
"../../../benchmarks/riscv_tests/rv32uf-p-fclass.hex",
"../../../benchmarks/riscv_tests/rv32uf-p-ldst.hex",
"../../../benchmarks/riscv_tests/rv32uf-p-fcvt.hex",
"../../../benchmarks/riscv_tests/rv32uf-p-fcvt_w.hex",
"../../../benchmarks/riscv_tests/rv32uf-p-move.hex",
"../../../benchmarks/riscv_tests/rv32uf-p-recoding.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-ldst.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-move.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-recoding.hex",
#endif
};
@@ -87,7 +87,7 @@ int main(int argc, char **argv)
simulator.load_ihex(test.c_str());
simulator.run();
bool status = (1 == simulator.get_status(28));
bool status = (1 == simulator.get_last_wb_value(3));
if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!status) std::cerr << RED << "Test Failed: " << test << std::endl;
@@ -108,7 +108,7 @@ int main(int argc, char **argv)
simulator.load_ihex(test.c_str());
simulator.run();
bool status = (1 == simulator.get_status(3));
bool status = (1 == simulator.get_last_wb_value(3));
if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!status) std::cerr << RED << "Test Failed: " << test << std::endl;
@@ -128,9 +128,6 @@ int main(int argc, char **argv)
#else
char test[] = "../../../runtime/tests/simple/vx_simple.hex";
//char test[] = "../../../benchmarks/riscv_tests/rv32ui-p-lb.hex";
//char test[] = "../../../benchmarks/riscv_tests/rv32ui-p-lw.hex";
//char test[] = "../../../benchmarks/riscv_tests/rv32ui-p-sw.hex";
std::cerr << test << std::endl;
@@ -140,7 +137,7 @@ int main(int argc, char **argv)
simulator.load_ihex(test);
simulator.run();
bool status = (1 == simulator.get_status(28));
bool status = (1 == simulator.get_last_wb_value(28));
if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!status) std::cerr << RED << "Test Failed: " << test << std::endl;