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floating point support fixes + riscv-tests update

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This commit is contained in:
Blaise Tine
2020-07-28 02:19:11 -04:00
parent e0a9089647
commit f01afcc5cd
338 changed files with 34269 additions and 36690 deletions
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42
hw/rtl/VX_fpu_unit.v
View File

@@ -59,10 +59,13 @@ module VX_fpu_unit #(
assign csr_to_fpu_if.warp_num = fpu_req_if.warp_num;
wire [`FRM_BITS-1:0] real_frm = (fpu_req_if.frm == `FRM_DYN) ? csr_to_fpu_if.frm : fpu_req_if.frm;
wire is_class_op_i, is_class_op_o;
assign is_class_op_i = (fpu_req_if.fpu_op == `FPU_CLASS);
reg [FOP_BITS-1:0] fpu_op;
reg [`FRM_BITS-1:0] fpu_rnd;
reg fpu_op_mod;
reg fflags_en, fflags_en_o;
reg fflags_en, fflags_en_o;
always @(*) begin
fpu_op = fpnew_pkg::SGNJ;
@@ -108,12 +111,10 @@ module VX_fpu_unit #(
endcase
end
`DISABLE_TRACING
fpnew_top #(
.Features (FPU_FEATURES),
.Implementation (FPU_IMPLEMENTATION),
.TagType (logic[`LOG2UP(`FPURQ_SIZE)-1+1:0])
.TagType (logic[`LOG2UP(`FPURQ_SIZE)-1+2:0])
) fpnew_core (
.clk_i (clk),
.rst_ni (1'b1),
@@ -125,19 +126,44 @@ module VX_fpu_unit #(
.dst_fmt_i (fpu_dst_fmt),
.int_fmt_i (fpu_int_fmt),
.vectorial_op_i (1'b1),
.tag_i ({fflags_en, fpu_in_tag}),
.tag_i ({fpu_in_tag, fflags_en, is_class_op_i}),
.in_valid_i (fpu_in_valid),
.in_ready_o (fpu_in_ready),
.flush_i (reset),
.result_o (fpu_result),
.status_o (fpu_status),
.tag_o ({fflags_en_o, fpu_out_tag}),
.tag_o ({fpu_out_tag, fflags_en_o, is_class_op_o}),
.out_valid_o (fpu_out_valid),
.out_ready_i (fpu_out_ready),
`UNUSED_PIN (busy_o)
);
`ENABLE_TRACING
reg [`NUM_THREADS-1:0][31:0] fpu_result_qual;
always @(8) begin
// unpack classify mask result
if (is_class_op_o) begin
integer i;
for (i = 0; i < `NUM_THREADS; i++) begin
integer l = i / 4;
integer w = i % 4;
integer class_mask = fpu_result[l][w * 8 +: 8];
fpu_result_qual[i][0] = class_mask[7] & class_mask[0];
fpu_result_qual[i][1] = class_mask[7] & class_mask[1];
fpu_result_qual[i][2] = class_mask[7] & class_mask[2];
fpu_result_qual[i][3] = class_mask[7] & class_mask[3];
fpu_result_qual[i][4] = class_mask[6] & class_mask[3];
fpu_result_qual[i][5] = class_mask[6] & class_mask[2];
fpu_result_qual[i][6] = class_mask[6] & class_mask[1];
fpu_result_qual[i][7] = class_mask[6] & class_mask[0];
fpu_result_qual[i][8] = class_mask[4];
fpu_result_qual[i][9] = class_mask[5];
end
end else begin
fpu_result_qual = fpu_result;
end
end
assign fpu_in_valid = fpu_req_if.valid;
assign fpu_in_tag = fpu_req_if.issue_tag;
@@ -146,7 +172,7 @@ module VX_fpu_unit #(
assign fpu_commit_if.valid = fpu_out_valid;
assign fpu_commit_if.issue_tag = fpu_out_tag;
assign fpu_commit_if.data = fpu_result;
assign fpu_commit_if.data = fpu_result_qual;
assign fpu_commit_if.upd_fflags = fflags_en_o;
assign fpu_commit_if.fflags_NV = fpu_status.NV;

6
hw/rtl/VX_writeback.v
View File

@@ -94,11 +94,11 @@ module VX_writeback #(
assign mul_commit_if.ready = !stall && !alu_valid && !lsu_valid && !csr_valid;
assign fpu_commit_if.ready = !stall && !alu_valid && !lsu_valid && !csr_valid && !mul_valid;
// special workaround to get RISC-V tests Pass status on Verilator
reg [31:0] last_data_wb [`NUM_REGS-1:0] /* verilator public */;
// special workaround to get RISC-V tests Pass/Fail status
reg [31:0] last_wb_value [`NUM_REGS-1:0] /* verilator public */;
always @(posedge clk) begin
if (writeback_tmp_if.valid && ~stall) begin
last_data_wb[writeback_tmp_if.rd] <= writeback_tmp_if.data[0];
last_wb_value[writeback_tmp_if.rd] <= writeback_tmp_if.data[0];
end
end

11
hw/simulate/simulator.cpp
View File

@@ -255,14 +255,11 @@ void Simulator::run() {
this->wait(5);
}
int Simulator::get_status(int reg) {
// check riscv-tests PASSED/FAILED status
#if (NUM_CLUSTERS == 1 && NUM_CORES == 1)
return (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_data_wb[reg];
#elif (NUM_CLUSTERS == 1)
return (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_data_wb[reg];
int Simulator::get_last_wb_value(int reg) {
#if (NUM_CLUSTERS == 1)
return (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
#else
return (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_data_wb[reg];
return (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg];
#endif
}

2
hw/simulate/simulator.h
View File

@@ -44,7 +44,7 @@ public:
void attach_ram(RAM* ram);
void run();
int get_status(int reg);
int get_last_wb_value(int reg);
void print_stats(std::ostream& out);
private:

127
hw/simulate/testbench.cpp
View File

@@ -9,70 +9,70 @@ int main(int argc, char **argv)
#ifdef ALL_TESTS
bool passed = true;
std::string tests[] = {/*
"../../../benchmarks/riscv_tests/rv32ui-p-add.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-addi.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-and.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-andi.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-auipc.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-beq.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-bge.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-bgeu.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-blt.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-bltu.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-bne.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-jal.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-jalr.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-lb.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-lbu.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-lh.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-lhu.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-lui.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-lw.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-or.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-ori.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sb.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sh.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-simple.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sll.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-slli.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-slt.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-slti.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sltiu.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sltu.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sra.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-srai.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-srl.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-srli.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sub.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-sw.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-xor.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-xori.hex",
std::string tests[] = {
"../../../benchmarks/riscv_tests/isa/rv32ui-p-add.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-addi.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-and.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-andi.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-auipc.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-beq.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bge.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bgeu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-blt.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bltu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bne.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-jal.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-jalr.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lb.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lbu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lh.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lhu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lui.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lw.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-or.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-ori.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sb.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sh.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-simple.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sll.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-slli.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-slt.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-slti.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sltiu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sltu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sra.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-srai.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-srl.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-srli.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sub.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sw.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-xor.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-xori.hex",
#ifdef EXT_M_ENABLE
"../../../benchmarks/riscv_tests/rv32um-p-div.hex",
"../../../benchmarks/riscv_tests/rv32um-p-divu.hex",
"../../../benchmarks/riscv_tests/rv32um-p-mul.hex",
"../../../benchmarks/riscv_tests/rv32um-p-mulh.hex",
"../../../benchmarks/riscv_tests/rv32um-p-mulhsu.hex",
"../../../benchmarks/riscv_tests/rv32um-p-mulhu.hex",
"../../../benchmarks/riscv_tests/rv32um-p-rem.hex",
"../../../benchmarks/riscv_tests/rv32um-p-remu.hex",
#endif*/
"../../../benchmarks/riscv_tests/isa/rv32um-p-div.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-divu.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mul.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mulh.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mulhsu.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mulhu.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-rem.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-remu.hex",
#endif
};
std::string tests_fp[] = {
#ifdef EXT_F_ENABLE
//"../../../benchmarks/riscv_tests/rv32uf-p-fadd.hex",
//"../../../benchmarks/riscv_tests/rv32uf-p-fdiv.hex",
//"../../../benchmarks/riscv_tests/rv32uf-p-fmadd.hex",
//"../../../benchmarks/riscv_tests/rv32uf-p-fmin.hex",
//"../../../benchmarks/riscv_tests/rv32uf-p-fcmp.hex",
"../../../benchmarks/riscv_tests/rv32uf-p-fclass.hex",
"../../../benchmarks/riscv_tests/rv32uf-p-ldst.hex",
"../../../benchmarks/riscv_tests/rv32uf-p-fcvt.hex",
"../../../benchmarks/riscv_tests/rv32uf-p-fcvt_w.hex",
"../../../benchmarks/riscv_tests/rv32uf-p-move.hex",
"../../../benchmarks/riscv_tests/rv32uf-p-recoding.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-ldst.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-move.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-recoding.hex",
#endif
};
@@ -87,7 +87,7 @@ int main(int argc, char **argv)
simulator.load_ihex(test.c_str());
simulator.run();
bool status = (1 == simulator.get_status(28));
bool status = (1 == simulator.get_last_wb_value(3));
if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!status) std::cerr << RED << "Test Failed: " << test << std::endl;
@@ -108,7 +108,7 @@ int main(int argc, char **argv)
simulator.load_ihex(test.c_str());
simulator.run();
bool status = (1 == simulator.get_status(3));
bool status = (1 == simulator.get_last_wb_value(3));
if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!status) std::cerr << RED << "Test Failed: " << test << std::endl;
@@ -128,9 +128,6 @@ int main(int argc, char **argv)
#else
char test[] = "../../../runtime/tests/simple/vx_simple.hex";
//char test[] = "../../../benchmarks/riscv_tests/rv32ui-p-lb.hex";
//char test[] = "../../../benchmarks/riscv_tests/rv32ui-p-lw.hex";
//char test[] = "../../../benchmarks/riscv_tests/rv32ui-p-sw.hex";
std::cerr << test << std::endl;
@@ -140,7 +137,7 @@ int main(int argc, char **argv)
simulator.load_ihex(test);
simulator.run();
bool status = (1 == simulator.get_status(28));
bool status = (1 == simulator.get_last_wb_value(28));
if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!status) std::cerr << RED << "Test Failed: " << test << std::endl;